參數(shù)資料
型號(hào): AD5764RBSUZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/32頁(yè)
文件大小: 0K
描述: IC DAC QUAD 16BIT VOUT 32-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5764(R), AD5744R Product Change 04/Sept/2009
設(shè)計(jì)資源: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006)
標(biāo)準(zhǔn)包裝: 500
設(shè)置時(shí)間: 8µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 275 mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 4 電壓,雙極
AD5764R
Data Sheet
Rev. D | Page 12 of 32
Pin No.
Mnemonic
Description
22
VOUTB
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 k, 200 pF load.
23
VOUTA
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 k, 200 pF load.
24
AGNDA
Ground Reference Pin for DAC A Output Amplifier.
25
REFAB
External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 7 V, and it
programs the full-scale output voltage. VREFIN = 5 V for specified performance.
26
REFCD
External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 7 V, and it
programs the full-scale output voltage. VREFIN = 5 V for specified performance.
27
REFOUT
Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ±
3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C.
28
REFGND
Reference Ground Return for the Reference Generator and Buffers.
29
TEMP
This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die
temperature; variation with temperature is 5 mV/°C.
32
BIN/2sCOMP
This pin determines the DAC coding. This pin should be hardwired to either DVCC or DGND. When hardwired to
DVCC, input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement
1
Internal pull-up device on this logic input. Therefore, it can be left floating; and it defaults to a logic high condition.
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