參數(shù)資料
型號： AD5764
廠商： Analog Devices, Inc.
英文描述： Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述： 完整，四路，16位，高精度，串行輸入，雙極性電壓輸出DAC
文件頁數(shù)： 20/27頁
文件大?。?/td> 251K
代理商： AD5764
Preliminary Technical Data
AD5764
DATA REGISTER
The Data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC Channel the Data
transfer is to take place (Refer to Table 7). The 16 data bits are in positions D15 to D0 as shown in Table 10.
Rev. PrC 21-Oct-04| Page 21 of 28
Table 10. Programming the Data Register
REG2
REG1
REG0
0
1
0
COARSE GAIN REGISTER
The Coarse Gain Register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC Channel the
Data transfer is to take place (Refer to Table 7). The Coarse Gain Register ia a 2-bit register and allows the user to select the output range
of each DAC as shown in Table 12.
A2
DAC Address
A1
A0
D15
D14
D13
D12
D11
D10
D9
16 Bit DAC Data
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 11. Programming the Coarse Gain Register
REG2
REG1
REG0
0
1
1
A2
DAC Address
A1
A0
D15 …. D2
Don’t Care
D1
CG1
D0
CG0
Table 12. Output Range Selection
Output Range
CG1
CG0
± 10 V
± 10.25 V
± 10.5 V
0
0
1
0
1
0
FINE GAIN REGISTER
The Fine Gain Register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC Channel the Data
transfer is to take place (Refer to Table 7). The Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each DAC
channel by -32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 13 and Table 14.
Table 13. Programming the Fine Gain Register
REG2
REG1
REG0
1
0
0
A2
DAC Address
A1
A0
D15 …. D6
Don’t Care
D5
FG5
D4
FG4
D3
FG3
D2
FG2
D1
FG1
D0
FG0
Table 14. Fine Gain Register Options
Gain Adjustment
+31 LSBs
+30 LSBs
No Adjustment
-31 LSBs
-32 LSBs
FG5
0
0
-
1
-
1
1
FG4
0
0
-
0
-
1
1
FG3
0
0
-
0
-
1
1
FG2
0
0
-
0
-
1
1
FG1
0
0
-
0
-
1
1
FG0
0
1
-
0
-
0
1
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