參數(shù)資料
型號(hào)： AD5762RCSUZ
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, MS-026ABA, TQFP-32
文件頁(yè)數(shù)： 24/33頁(yè)
文件大?。?/td> 507K
代理商： AD5762RCSUZ
AD5762R
Preliminary Technical Data
Table 7. AD5762R Input Register Format
MSB
DB23
DB22
DB21
DB20
R/W
0
REG2
REG1
Rev. PrA | Page 24 of 33
DB19
REG0
DB18
A2
DB17
A1
DB16
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DATA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
LSB
DB0
Table 8. Input Register Bit Functions
Register
R/W
REG2, REG1, REG0
Function
Indicates a read from or a write to the addressed register.
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register.
REG2
REG1
REG0
Function
0
0
0
Function Register
0
1
0
Data Register
0
1
1
Coarse Gain Register
1
0
0
Fine Gain Register
1
0
1
Offset Register
These bits are used to decode the DAC channels.
A2
A1
A0
Channel Address
0
0
0
DAC A
0
0
1
DAC B
1
0
0
BOTH DACs
Data Bits.
A2, A1, A0
D15:D0
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 9 and Table 10.
Table 9. Function Register Options
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
0
0
0
0
0
0
0
0
0
0
0
1
Don’t Care
Local-
Ground-
Offset Adjust
0
0
0
1
0
0
0
0
0
1
0
1
DB4
NOP, Data = Don’t Care
D1 Direction
DB3
DB2
DB1
DB0
D1
Value
D0
Direction
D0
Value
SDO
Disable
CLR, Data = Don’t Care
LOAD, Data = Don’t Care
Table 10. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local-Ground-
Offset Adjust
function (default). Refer to Features section for further details.
D0/D1
Direction
section for further details.
D0/D1 Value
I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When
enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
CLR
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
LOAD
Addressing this function updates the DAC registers and consequently the analog outputs.
Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the Features
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