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參數(shù)資料
| 型號： | AD5754RBREZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DSP/SRL 24TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設計資源： | Software Configurable 16-Bit Quad-Channel Unipolar/Bipolar Voltage Output Using AD5754R (CN0083) |
| 標準包裝： | 1 |
| 設置時間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 310mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm）裸露焊盤 |
| 供應商設備封裝： | 24-TSSOP 裸露焊盤 |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 784 (CN2011-ZH PDF) |
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AD5724R/AD5734R/AD5754R
Rev. E | Page 21 of 32
Standalone Operation
The serial interface works with both a continuous and a
noncontinuous serial clock. A continuous SCLK source can
only be used if SYNC is held low for the correct number of
clock cycles. In gated clock mode, a burst clock containing the
exact number of clock cycles must be used, and SYNC must be
taken high after the final clock to latch the data. The first falling
edge of SYNC starts the write cycle. Exactly 24 falling clock
edges must be applied to SCLK before SYNC is brought high
again. If SYNC is brought high before the 24th falling SCLK
edge, the data written is invalid. If more than 24 falling SCLK
edges are applied before SYNC is brought high, the input data
is also invalid. The input register addressed is updated on the
rising edge of SYNC. For another serial transfer to take place,
SYNC must be brought low again. After the end of the serial
data transfer, data is automatically transferred from the input
shift register to the addressed register.
When the data has been transferred into the chosen register
of the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low while SYNC is high.
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11*
MISO
SDIN
SCLK
MOSI
SCK
PC7
PC6
SDO
SCLK
SDO
SCLK
SDO
SDIN
SYNC
LDAC
AD5724R/
AD5734R/
AD5754R*
AD5724R/
AD5734R/
AD5754R*
AD5724R/
AD5734R/
AD5754R*
06
46
5-
0
08
Figure 46. Daisy Chaining the AD5724R/AD5734R/AD5754R
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
of serial interface lines. The first falling edge of SYNC starts the
write cycle. SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears
on the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5724R/AD5734R/AD5754R devices in the chain. When the
serial transfer to all devices is complete, SYNC is taken high.
This latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or gated clock.
A continuous SCLK source can only be used if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
Readback Operation
Readback mode is invoked by setting the R/W bit to 1 in the
write operation to the serial input shift register. (If the SDO
output is disabled via the SDO disable bit in the control register,
it is automatically enabled for the duration of the read operation,
after which it is disabled again.) With R/W set to 1, Bit A2 to Bit
A0 in association with Bit REG2 to Bit REG0 select the register
to be read. The remaining data bits in the write sequence are don’t
care bits. During the next SPI write, the data appearing on the
SDO output contains the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO. The readback diagram in
shows the readback
sequence. For example, to read back the DAC register of
Channel A, the following sequence should be implemented:
1.
Write 0x800000 to the AD5724R/AD5734R/AD5754R
input register. This configures the part for read mode
with the DAC register of Channel A selected. Note that
all the data bits, DB15 to DB0, are don’t care bits.
2.
Follow this with a second write, a NOP condition, 0x180000.
During this write, the data from the register is clocked out
on the SDO line.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD5754RBREZ-REEL7 | 功能描述:IC DAC 16BIT DSP/SRL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5755 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA |
| AD5755_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control |
| AD5755-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA and Voltage Output DAC,Dynamic Power Control |
| AD5755-1_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA and Voltage Output DAC,Dynamic Power Control |
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