參數(shù)資料
型號(hào)： AD5752RBREZ
廠商： Analog Devices Inc
文件頁數(shù)： 2/32頁
文件大?。?/td> 0K
描述： IC DAC DUAL 16BIT SERIAL 24TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Software Configurable 16-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5752R (CN0089)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 10µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 190mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm）裸露焊盤
供應(yīng)商設(shè)備封裝： 24-TSSOP 裸露焊盤
包裝： 管件
輸出數(shù)目和類型： 2 電壓，單極；2 電壓，雙極
采樣率（每秒）： 1.07M
產(chǎn)品目錄頁面： 784 (CN2011-ZH PDF)
AD5722R/AD5732R/AD5752R
Rev. D | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5722R/
AD5732R/
AD5752R
CLR
LDAC
AVSS
NC
VOUTA
NC
SYNC
NC
BIN/2sCOMP
GND
SDO
REFIN/REFOUT
SIG_GND
SCLK
SDIN
NC
NOTES
1. NC = NO CONNECT
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL PERFORMANCE.
AVDD
VOUTB
NC
SIG_GND
DAC_GND
DVCC
NC
TOP VIEW
(Not to Scale)
06
46
6-
0
5
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
AVSS
Negative Analog Supply. Voltage ranges from 4.5 V to 16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
2, 4, 6, 12,
13, 22
NC
Do not connect to these pins.
3
VOUTA
Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
5
BIN/2sCOMP
Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND.
When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary.)
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
8
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
LDAC
Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When
this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is
held high during the write cycle, the DAC input register is updated, but the output update is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of
LDAC. The LDAC pin should not be left unconnected.
11
CLR
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable).
14
DVCC
Digital Supply. Voltage ranges from 2.7 V to 5.5 V.
15
GND
Ground Reference.
16
SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
17
REFIN/REFOUT
External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.
REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV.
18, 19
DAC_GND
Ground Reference for the Four Digital-to-Analog Converters.
20, 21
SIG_GND
Ground Reference for the Four Output Amplifiers.
23
VOUTB
Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
24
AVDD
Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V.
Exposed
Paddle
This exposed paddle should be connected to the potential of the AVSS pin, or alternatively, it can be left electrically
unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal
performance.
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