Referring to Figure 1, RSET is a" />
參數(shù)資料
型號(hào)： AD5748ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 0K
描述： IC I/V OUTPUT DRIVER 32LFCSP
標(biāo)準(zhǔn)包裝： 1
放大器類型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 2 V/µs
電流 - 輸出 / 通道： 15mA
電壓 - 電源，單路/雙路(±)： ±12 V ~ 24 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 管件
AD5748
Rev. A | Page 29 of 32
CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor as part of
the voltage-to-current conversion circuitry. The nominal value
of the internal current sense resistor is 15 kΩ. To allow for over-
range capability in current mode, the user can also select the
internal current sense resistor to be 14.7 kΩ, giving a nominal
2% overrange capability. This feature is available in the 0 mA
to 21 mA and 4 mA to 21 mA current ranges.
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature,
an external low drift resistor can be connected to the REXT1
and REXT2 pins of the AD5748, which can be used instead of
the internal resistor. The external resistor is selected via the
input shift register. If the external resistor option is not used,
the REXT1 and REXT2 pins should be left floating.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5748 offers the option of error checking based on
an 8-bit (CRC-8) cyclic redundancy check. The device controlling
the AD5748 should generate an 8-bit frame check sequence
using the following polynomial:
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5748 before taking SYNC high. If the AD5748
receives a 24-bit data frame, it performs the error check when
SYNC goes high. If the check is valid, then the data is written
to the selected register. If the error check fails, the FAULT pin
goes low and Bit D3 of the status register is set. After reading
this register, this error flag is cleared automatically and the
FAULT pin goes high again.
SCLK
SDIN
SYNC
UPDATE ON SYNC HIGH
D15
(MSB)
D0
(LSB)
16-BIT DATA
16-BIT DATA TRANSER—NO ERROR CHECKING
SCLK
SDIN
SYNC
FAULT
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
FAULT GOES LOW IF
ERROR CHECK FAILS
D23
(MSB)
D8
(LSB)
D7
D0
16-BIT DATA
8-BIT FCS
16-BIT DATA TRANSER WITH ERROR CHECKING
089
22-
055
Figure 53. PEC Error Checking Timing
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