參數(shù)資料
型號： AD5744R
廠商： Analog Devices, Inc.
英文描述： Complete Quad, 14-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述： 完整的四，14位，高精度，串行輸入，雙極性電壓輸出DAC
文件頁數(shù)： 22/32頁
文件大?。?/td> 489K
代理商： AD5744R
AD5744R
Preliminary Technical Data
Rev. PrA | Page 22 of 32
V
OUT
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
14-BIT
DAC
V
REFIN
SYNC
INPUT
REGISTER
SCLK
0
The output voltage expression for the AD5744R is given by
×
+
×
=
16384
4
2
D
V
V
V
REFIN
REFIN
OUT
where:
D
is the decimal equivalent of the code loaded to the DAC.
V
REFIN
is the reference voltage applied at the REFAB/REFCD
pins.
ASYNCHRONOUS CLEAR (CLR)
Figure 37. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 3) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If at power-on CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5744R.
TRANSFER FUNCTION
Table 6
shows the ideal input code to output voltage
relationship for the AD5744R for both offset binary and twos
complement data coding.
Table 6. Ideal Output Voltage to Input Code Relationship for
the AD5744R
Digital Input
Offset Binary Data Coding
Analog Output
V
OUT
+2 V
REF
× (8191/8192)
+2 V
REF
× (1/8192)
0 V
2 V
REF
× (1/8192)
2 V
REF
× (8191/8192)
V
OUT
+2 V
REF
× (8191/8192)
+2 V
REF
× (1/8192)
0 V
2 V
REF
× (1/8192)
2 V
REF
× (8191/8192)
MSB
11
10
10
01
00
Twos Complement Data Coding
MSB
01
1111
00
0000
00
0000
11
1111
10
0000
LSB
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
LSB
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
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