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參數(shù)資料
| 型號： | AD5732R |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad 12-Bit Serial Input Unipolar/Bipolar Voltage Output DAC |
| 中文描述： | 四路12位串行輸入單極性/雙極性電壓輸出DAC |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 405K |
| 代理商： | AD5732R |
AD5726
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 20
AV
DD
V
OUTD
V
OUTC
V
REFN
V
REFP
V
OUTB
V
OUTA
AV
SS
1
2
3
4
CLRSEL
CLR
LDAC
NC
CS
SCLK
SDIN
GND
16
15
14
13
5
6
7
12
11
10
8
9
NC = NO CONNECT
Figure 5. Pin Configuration
TOP VIEW
(Not to Scale)
AD5726
0
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
1
AV
DD
2
V
OUTD
3
V
OUTC
4
V
REFN
Description
Positive Analog Supply Pin. Voltage ranges from 5 V to 15 V
Buffered Analog Output Voltage of DAC D.
Buffered Analog Output Voltage of DAC C.
Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output.
Allowable range is AV
SS
to V
REFP
2.5 V.
Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage.
Allowable range is A
VDD
2.5 V to V
REFN
+ 2.5 V.
Buffered Analog Output Voltage of DAC B.
Buffered Analog Output Voltage of DAC A.
Negative Analog Supply Pin. Voltage ranges from 0 V to 15 V.
Ground Reference Pin.
Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored when CS is high.
Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.
Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin is logically OR’ed with
the SCLK input and disables the serial data input when high.
No Internal Connection.
Active Low, Asynchronous Load DAC Input. The data currently contained in the serial input register is
transferred out to the DAC data registers on the falling edge of LDAC, independent of CS. Input data must
remain stable while LDAC is low.
Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or midscale (0x800),
depending on the state of CLRSEL. The data in the serial input register is unaffected by this control.
Determines the action of CLR. If high, a clear command sets the internal DAC registers to midscale (0x800).
If low, the registers are set to zero (0x000).
5
V
REFP
6
7
8
9
10
11
12
V
OUTB
V
OUTA
AV
SS
GND
SDIN
SCLK
CS
13
14
NC
LDAC
15
CLR
16
CLRSEL
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