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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD5726YRWZ-REEL |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 17/20闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 12BIT QUAD SERIAL 16-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 绯诲垪锛� | iCMOS® |
| 瑷�(sh猫)缃檪闁擄細 | 9µs |
| 浣嶆暩(sh霉)锛� | 12 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 30mW 鍠サ锛�240mW 闆欐サ |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 4 闆诲锛屽柈妤�锛�4 闆诲锛岄洐妤� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�鐣�(d膩ng)鍓嶇17闋�绗�18闋�绗�19闋�绗�20闋�
AD5726
Data Sheet
Rev. C | Page 6 of 20
TIMING CHARACTERISTICS
AVDD = +15 V or +5 V, AVSS = 15 V or 5 V or 0 V, GND = 0 V; VREFP = +10 V or +2.5 V; VREFN = 10 V or 2.5 V or 0 V, RLOAD = 2 k惟,
Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
tDS
5
ns
Data setup time
tDH
5
ns
Data hold time
tCH
13
ns
Clock pulse width high
tCL
13
ns
Clock pulse width low
tCSS
13
ns
Select time
tCSH
13
ns
Deselect delay
tLD1
20
ns
Load disable time
tLD2
20
ns
Load delay
tLDW
20
ns
Load pulse width
tCLRW
20
ns
Clear pulse width
1 Guaranteed by design and characterization, not production tested.
2 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Timing Diagrams
CS
SDIN
SCLK
LDAC
tCSS
tLD1
tCSH
tLD2
A1
A0
X
D11
D10
D9
D8
D4
D3
D2
D1
D0
06
46
9-
0
02
Figure 2. Data Load Sequence
SDIN
SCLK
VOUT
CS
LDAC
tDS
tCL
tCH
tCSH
tLD2
tLDW
tS
tDH
卤1LSB
0
64
69
-00
3
Figure 3. Data Load Timing
CLRSEL
VOUT
CLR
tCLRW
tS
卤1LSB
0
64
69
-00
4
Figure 4. Clear Timing
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| AD5726YRWZ-REEL7 | 鍔熻兘鎻忚堪:IC DAC 12BIT QUAD SERIAL 16-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:iCMOS® 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 瑷�(sh猫)缃檪闁�:4µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-uMAX 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:2 闆诲锛屽柈妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鐢�(ch菐n)鍝佺洰閷勯爜闈�:1398 (CN2011-ZH PDF) |
| AD572AD | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪: 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:12-BIT ADC IC - Bulk 鍒堕€犲晢:AD 鍔熻兘鎻忚堪:_ |
| AD572B | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:12-BIT SUCCESSIVE APPROXIMATION INTEGRATED CIRCUIT A/D CONVERTER |
| AD572BD | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
| AD572S | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:12-BIT SUCCESSIVE APPROXIMATION INTEGRATED CIRCUIT A/D CONVERTER |
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