AVDD = +5 V ± 5%, AV
參數(shù)資料
型號: AD5726YRSZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: IC DAC 12BIT QUAD SERIAL 16-SSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
系列: iCMOS®
設(shè)置時間: 9µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 30mW 單極;240mW 雙極
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 標準包裝
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
其它名稱: AD5726YRSZ-REELDKR
Data Sheet
AD5726
Rev. C | Page 3 of 20
SPECIFICATIONS
AVDD = +5 V ± 5%, AVSS = 0 V or 5 V ± 5%, VREFP = +2.5 V, VREFN = 0 V or 2.5 V, RLOAD = 2 k. All specifications TMIN to TMAX, unless
otherwise noted.1
Table 1.
Parameter
Value
Unit
Test Conditions/Comments
ACCURACY
Resolution
12
Bits
Relative Accuracy (INL)
±1
LSB max
Y grade, AVSS = 5 V, outputs unloaded
±1
LSB max
Y grade, AVSS = 0 V2
Differential Nonlinearity (DNL)
±1
LSB max
Guaranteed monotonic
Linearity Matching
±1
LSB typ
Zero-Scale Error
±6
LSB max
AVSS = 5 V
Full-Scale Error
±6
LSB max
AVSS = 5 V
Zero-Scale Error
±12
LSB max
AVSS = 0 V2
Full-Scale Error
±12
LSB max
AVSS = 0 V2
Zero-Scale TemperatureCoefficient3
±10
ppm FSR/°C typ
AVSS = 5 V
Full-Scale Temperature Coefficient3
±10
ppm FSR/°C typ
AVSS = 5 V
REFERENCE INPUT
VREFP
Reference Input Range4
VREFN + 2.5
V min
AVDD 2.5
V max
Input Current
±0.75
mA max
Typically 0.25 mA
VREFN
Reference Input Range4
AVSS
V min
0 V
V min
AVSS = 0 V
VREFP 2.5
V max
Input Current
1.0
mA max
Typically 0.6 mA, AVSS = 5 V
Large Signal Bandwidth3
160
kHz typ
3 dB, VREFP = 0 V to 10 V p-p
OUTPUT CHARACTERISTICS3
Output Current
±1.25
mA max
AVSS = 5 V
DIGITAL INPUTS
Input High Voltage, VIH
2.4
V min
Input Low Voltage, VIL
0.8
V max
Input Current3
10
A max
Input Capacitance3
5
pF typ
POWER SUPPLY CHARACTERISTICS
Power Supply Sensitivity3
0.002
%/% max
Typically 0.0004%/%
AIDD
1.5
mA/channel max
Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V
AISS
1.5
mA/channel max
Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V
Power Dissipation
30
mW max
Outputs unloaded, typically 15 mW, AVSS = 0 V
1
All supplies can be varied ±5% and operation is guaranteed. Device is tested with AVDD = 4.75V.
2
For single-supply operation (VREFN = 0 V, AVSS = 0 V), due to internal offset errors, INL and DNL are measured beginning at Code 0x005.
3
Guaranteed by design and characterization, not production tested.
4
Operation is guaranteed over this reference range,but linearity is neither tested nor guaranteed.
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