TA = 25°C, un" />
參數(shù)資料
型號： AD5700-1ACPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 21/24頁
文件大?。?/td> 0K
描述： IC HART MODEM LP INT OSC 24LFCSP
標(biāo)準(zhǔn)包裝： 1,500
系列： *
AD5700/AD5700-1
Data Sheet
Rev. F | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4.
Parameter
Rating
VCC to GND
0.3 V to +7 V
IOVCC to GND
0.3 V to +7 V
Digital Inputs to DGND
0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
Digital Output to DGND
0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
HART_OUT to AGND
0.3 V to +2.5 V
HART_IN to AGND
0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
ADC_IP
0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
AGND to DGND
0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial
40°C to +125°C
Storage Temperature Range
65°C to +150°C
Junction Temperature (TJ MAX)
150°C
Power Dissipation
(TJ MAX – TA)/θJA
Lead Temperature,
JEDEC industry standard
Soldering
J-STD-020
ESD
Human Body Model
(ANSI/ESDA/JEDEC JS-001-
2010)
8 kV
Field Induced Charge Model
(JEDEC JESD22_C101E)
1.5 kV
Machine Model
(ANSI/ESD S5.2-2009)
400 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
θJA1
θJC
Unit
24-Lead LFCSP
56
3
°C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. See JEDEC JESD51.
ESD CAUTION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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