參數(shù)資料
型號(hào): AD569KNZ
廠商: Analog Devices Inc
文件頁數(shù): 6/12頁
文件大小: 0K
描述: IC DAC 16BIT MONOTONIC 28-DIP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 13
設(shè)置時(shí)間: 4µs
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 28-PDIP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
AD569
REV. A
–3–
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance Only and are not subject to test.
+VS = +12 V; –VS = –12 V; +VREF = +5 V; –VREF = –5 V excepts where stated.
Parameter
Limit
Units
Test Conditions/Comments
Output Voltage Settling
5
s max
No Load Applied
(Time to
±0.001% FS
3
s typ
(DAC output measured from falling edge of LDAC.)
For FS Step)
6
s max
VOUT Load = 1 k, CLOAD = 1000 pF.
4
s typ
(DAC output measured from falling edge of LDAC. )
Digital-to-Analog Glitch
500
nV-sec typ
Measured with VREF = 0 V. DAC registers alternatively loaded
Impulse
with input codes of 8000H and 0FFFH (worst-case
transition). Load = 1 k
.
Multiplying Feedthrough
–100
dB max
+VREF = 1 V rms 10 kHz sine wave,
–VREF = 0 V
Output Noise Voltage
40
nV/
Hz
typ
Measured between VOUT and –VREF
Density (1 kHz-1 MHz)
TIMING CHARACTERISTICS (+VS = +12 V, –VS = –12 V, VIH = 2.4 V, VIL = 0.4 V,TMIN to TMAX)
Parameter
Limit
Units
Test Conditions/Comments
Case A
150 ns Pulse on HBE, LBE, and LDAC
THS = 140 ns min, THH = 10 ns min
tWC
120
ns min
CS
Pulse Width
tSC
60
ns min
CS
Data Setup Time
tHC
20
ns min
CS
Data Hold Time
Case B
None
tWB
70
ns min
HBE
, LBE Pulse Width
tSB
80
ns min
HBE
, LBE Data Setup Time
tHB
20
ns min
HBE
, LBE Data Hold Time
tSCS
120
ns min
CS
Setup Time
tHCS
10
ns min
CS
Hold Time
tWD
120
ns min
LDAC
Pulse Width
Case C
None
tWB
120
ns min
HBE
, LBE Pulse Width
tSB
80
ns min
HBE
, LBE Data Setup Time
tHB
20
ns min
HBE
, LBE Data Hold Time
tSCS
120
ns min
CS
Setup Time
tHCS
10
ns min
CS
Hold Time
Figure 2a. AD569 Timing Diagram – Case B
Figure 2b. AD569 Timing Diagram – Case C
Figure 1. AD569 Timing Diagram – Case A
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