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參數(shù)資料
| 型號(hào)： | AD569KN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Bit Monotonic Voltage Output D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 468K |
| 代理商： | AD569KN |
AD569
REV. A
–3–
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance Only and are not subject to test.
+V
S
= +12 V; –V
S
= –12 V; +V
REF
= +5 V; –V
REF
= –5 V excepts where stated.
Parameter
Limit
Units
Test Conditions/Comments
Output Voltage Settling
(Time to
±
0.001% FS
For FS Step)
5
3
6
4
μ
s max
μ
s typ
μ
s max
μ
s typ
No Load Applied
(DAC output measured from falling edge of
LDAC
.)
V
OUT
Load = 1 k
, C
LOAD
= 1000 pF.
(DAC output measured from falling edge of
LDAC.
)
Digital-to-Analog Glitch
Impulse
500
nV-sec typ
Measured with V
REF
= 0 V. DAC registers alternatively loaded
with input codes of 8000
H
and 0FFF
H
(worst-case
transition). Load = 1 k
.
Multiplying Feedthrough
–100
dB max
+V
REF
= 1 V rms 10 kHz sine wave,
–V
REF
= 0 V
Output Noise Voltage
Density (1 kHz-1 MHz)
40
nV/
Hz
typ
Measured between V
OUT
and –V
REF
TIMING CHARACTERISTICS
(+V
S
= +12 V, –V
S
= –12 V, V
IH
= 2.4 V, V
IL
= 0.4 V,T
MIN
to T
MAX
)
Parameter
Limit
Units
Test Conditions/Comments
Case A
150 ns Pulse on
HBE
,
LBE
, and
LDAC
T
HS
= 140 ns min, T
HH
= 10 ns min
CS
Pulse Width
CS
Data Setup Time
CS
Data Hold Time
None
HBE
,
LBE
Pulse Width
HBE
,
LBE
Data Setup Time
HBE
,
LBE
Data Hold Time
CS
Setup Time
CS
Hold Time
LDAC
Pulse Width
None
HBE
,
LBE
Pulse Width
HBE
,
LBE
Data Setup Time
HBE
,
LBE
Data Hold Time
CS
Setup Time
CS
Hold Time
t
WC
t
SC
t
HC
Case B
t
WB
t
SB
t
HB
t
SCS
t
HCS
t
WD
Case C
t
WB
t
SB
t
HB
t
SCS
t
HCS
120
60
20
ns min
ns min
ns min
70
80
20
120
10
120
ns min
ns min
ns min
ns min
ns min
ns min
120
80
20
120
10
ns min
ns min
ns min
ns min
ns min
Figure 2a. AD569 Timing Diagram – Case B
Figure 2b. AD569 Timing Diagram – Case C
Figure 1. AD569 Timing Diagram – Case A
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