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參數(shù)資料
| 型號： | AD569JPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT MONO NON-LIN 28PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
AD569
REV. A
–10–
Table I. AD569 Truth Table
CS
HBE
LBE
LDAC
OPERATION
1
X
No Operation
X
1
No Operation
0
1
Enable 8 MSBs of First Rank
0
1
0
1
Enable 8 LSBs of First Rank
0
1
0
Enable 16-Bit DAC Register
0
All Latches Transparent
All four control inputs latches are level-triggered and active low.
When the DAC register is loaded directly from a bus, the data at
the digital inputs will be reflected in the output any time CS,
LDAC
, LBE and HBE are low. Should this not be the desired
case, bring LDAC (or HBE or LBE) high before changing the
data. Alternately, use a second write cycle to transfer the data to
the DAC register or delay the write strobe pulse until the appro-
priate data is valid. Be sure to observe the appropriate data
setup and hold times (see Timing Characteristics).
Whenever possible, the write strobe signal should be applied to
HBE
and LBE with the AD569’s decoded address applied to
CS
. A minimum pulse width of 60 ns at HBE and LBE allows
the AD569 to interface to the fastest microprocessors. Actually,
data can be latched with narrower pulses, but the data setup and
hold times must be lengthened.
16-Bit Microprocessor Interfaces
Since 16-bit microprocessors supply the AD569’s complete 16-
bit input in one write cycle, the DAC register is often unneces-
sary. If so, it should be made transparent by grounding LDAC.
The DAC’s decoded address should be applied to CS, with the
write strobe applied to HBE and LBE as shown in the 68000 in-
terface in Figure 19.
Figure 19. AD569/68000 Interface
DIGITAL CIRCUIT CONNECTIONS
The AD569’s truth table appears in Table I. The High Byte En-
able (HBE) and Low Byte Enable (LBE) inputs load the upper
and lower bytes of the 16-bit input when Chip Select (CS) is
valid (low). A similar strobe to Load DAC (LDAC) loads the
16-bit input into the DAC register and completes the DAC up-
date. The DAC register can either be loaded with a separate
write cycle or synchronously with either of the 8-bit registers in
the first rank. A simultaneous update of several AD569s can be
achieved by controlling their LDAC inputs with a single control
signal.
under worst-case conditions (hex input code 0000), feedthrough
remains below –100 dB at ac reference frequencies up to 10 kHz.
Figure 16. Multiplying Feedthrough
BYPASSING AND GROUNDING RULES
It is generally considered good engineering practice to use bypass
capacitors on the device supply voltage pins and to insert small
valued resistors in the supply lines to provide a measure of decou-
pling between various circuits in a system. For the AD569, bypass
capacitors of at least 4.7
F and series resistors of 10 are recom-
mended. The supply voltage pins should be decoupled to Pin 18.
NOISE
In high-resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 152
V
(–96 dB). Therefore, the noise floor must remain below this
level in the frequency ranges of interest. The AD569’s noise
spectral density is shown in Figures 17 and 18. The lowband
noise spectrum in Figure 17 shows the 1/f corner frequency at
1.2 kHz and Figure 18 shows the wideband noise to be below
40 nV/
Hz
.
Figure 17. Lowband Noise Spectrum
Figure 18. Wideband Noise Spectrum
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