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參數(shù)資料
| 型號(hào)： | AD568K |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Ultrahigh Speed Monolithic D/A Converter |
| 中文描述： | 12位超高速單片D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 541K |
| 代理商： | AD568K |
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AD568
REV. A
–7–
The threshold of the digital inputs is set at 1.4 V and does not
vary with supply voltage. This is provided by a bandgap refer-
ence generator, which requires approximately 3 mA of bias cur-
rent achieved by tying R
TH
to any +V
L
supply where
R
TH
=
+
V
L
–1.4
V
3
mA
The input lines operate with small input currents to easily
achieve interface with unbuffered CMOS logic. The digital in-
put signals to the DAC should be isolated from the analog out-
put as much as possible. To minimize undershoot, ringing, and
possible digital feedthrough noise, the interconnect distances to
the DAC inputs should be kept as short as possible. Termina-
tion resistors may improve performance if the digital lines be-
come too long. The digital input should be free from large
glitches and ringing and have maximum 10% to 90% rise and
fall times of 5 ns. Figure 12 shows the equivalent digital input
circuit of the AD568.
1.28mA
125
R
(EXTERNAL)
V
THRESHOLD
1.4V
BANDGAP
DIODE
THRESHOLD
COMMON
LADDER
COMMON
TO
I
OUT
TO ANALOG
COMMON
TO
THRESHOLD
COMMON
+V
L
5pF
BIT
INPUT
58pF
Figure 12. Equivalent Digital Input
Due to the high-speed nature of the AD568, it is recommended
that high-speed logic families such as Schottky TTL, high-speed
CMOS, or the new lines of FAST* TTL be used exclusively.
Table I shows how DAC performance can vary depending on
the driving logic used. As this table indicates, STTL, HCMOS,
and FAST represent the most viable families for driving the
AD568.
Table I. DAC Performance vs. Drive Logic
1
DAC
10-90%
DAC
Rise Time
2
Settling Time
2, 3
1%
0.1%
Maximum
Glitch
Excursion
Logic
Family
0.025%
Glitch
4
Impulse
TTL
LSTTL
STTL
HCMOS 11 ns
FAST*
11 ns
11 ns
9.5 ns
18 ns
28 ns
16 ns
24 ns
16 ns
34 ns
46 ns
33 ns
38 ns
36 ns
50 ns
80 ns
50 ns
50 ns
42 ns
2.5 nV-s
950 pV-s
850 pV-s
350 pV-s
1.0 nV-s
240 mV
160 mV
150 mV
115 mV
250 mV
12 ns
NOTES
1
All values typical, taken in rest fixture diagrammed in Figure 13.
2
Measurements are made for a 1 V full-scale step into 100
DAC load
resistance.
3
Settling time is measured from the time the digit input crosses the threshold
voltage (1.4 V) to when the output is within the specified range of its final
value.
4
The worst case glitch impulse, measured on the major carry DAC full scale
is 1 V.
mode, the DAC output scale is insensitive to whether the load
resistor, R
L
, is shorted (Pin 19 connected to Pin 20), or
grounded (Pin 19 connected to Pin 18). However, this does
affect the output impedance of the DAC current and may have a
significant impact on the noise gain of the external circuitry. In
the voltage output mode, the DAC’s output current flows
through its own internal impedance (perhaps in parallel with an
external impedance) to generate a voltage, as in Figures 3, 4, 5,
and 10. In this case, the DAC output scale is directly dependent
on the load impedance. The temperature coefficient of the
AD568’s internal reference is trimmed in such a way that the
drift of the DAC output in the voltage output mode is centered
on zero. The current output of the DAC will have an additional
drift factor corresponding to the absolute temperature coeffi-
cient of the internal thin-film resistors. This additional drift may
be removed by judicious placement of the 1 k
span resistor in
the signal path. For example, in Figures 8 and 9, the current
flowing from the DAC into the summing junction could suffer
from as much as 150 ppm/
°
C of thermal drift. However, since
this current flows through the internal span resistor (Pins 15 and
16) which has a temperature coefficient that matches the DAC
ladder resistors, this drift factor is compensated and the buffered
voltage at the amplifier output will be within specified limits for
the voltage output mode.
Output Voltage Compliance
The AD568 has a typical output compliance range of +1.2 V to
–2.0 V (with respect to the LCOM Pin). The current-
steering output stages will be unaffected by changes in the out-
put terminal voltage over that range. However, as shown in Fig-
ure 11, there is an equivalent output impedance of 200
in
parallel with 15 pF at the output terminal which produces an
equivalent error current if the voltage deviates from the ladder
common. This is a linear effect which does not change with in-
put code. Operation beyond the maximum compliance limits
may cause either output stage saturation or breakdown resulting
in nonlinear performance. The positive compliance limit is not
affected by the positive power supply, but is a function of output
current and the logic threshold voltage at V
TH
, Pin 13.
I
OUT
= 10.24mA xDI4096
I
OUT
= 10.24mA x
10.24mA
R
(200
)
15pF
ANALOG
COMMON
LADDER
COMMON
R
(200
)
15pF
COMPLIANCE
TO V
THRESHOLD
R
LOAD
I
OUT
R
LADDER
)
COMPLIANCE TO
LOGIC LOW VALUE
(
1 – DI4096
)
Figure 11. Equivalent Output
Digital Input Considerations
The AD568 uses a standard positive true straight binary code
for unipolar outputs (all 1s full-scale output), and an offset bi-
nary code for bipolar output ranges. In the bipolar mode, with
all 0s on the inputs, the output will go to negative full scale;
with 111 . . . 11, the output will go to positive full scale less
1 LSB; and with 100 . . 00 (only the MSB on), the output will
go to zero.
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