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參數(shù)資料
| 型號(hào)： | AD5663ARMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 220k |
| 配用： | EVAL-AD5663REBZ-ND - BOARD EVAL FOR AD5663 |
AD5663
Rev. 0 | Page 16 of 24
POWER-DOWN MODES
The AD5663 contains four separate modes of operation.
Command 100 is reserved for the power-down function
(see Table 7). These modes are software-programmable by
setting Bit DB5 and Bit DB4 in the control register. Table 11
shows how the state of the bits corresponds to the mode of
operation of the device. Any or all DACs (DAC B and DAC A)
can be powered down to the selected mode by setting the
corresponding two bits (Bit DB1 and Bit DB0) to 1. By
executing the same Command 100, any combination of DACs
can be powered up by setting Bit DB5 and Bit DB4 to normal
operation mode. Again, to select which combination of DAC
channels to power up, set the corresponding two bits (Bit DB1
and Bit DB0) to 1. See Table 12 for contents of the input shift
register during power-down/power-up operation.
The DAC output powers up to the value in the input register
while LDAC is low. If LDAC is high, the DAC output powers up
to the value held in the DAC register before power-down.
When both bits are set to 0, the part works normally with its
normal power consumption of 500 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (100 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ or 100 kΩ register
or left open-circuited (three-state) (see Figure 31).
RESISTOR
NETWORK
VOUT
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
05
85
5-
0
36
Figure 31. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down.
The time required to exit power-down is typically 4 μs for
Table 11. Power-Down Modes of Operation for the AD5663
DB5
DB4
Operating Mode
0
Normal operation
Power-Down Modes
0
1
1 kΩ to GND
1
0
100 kΩ to GND
1
Three-state
LDAC FUNCTION
The AD5663 DAC has double-buffered interfaces consisting of
two banks of registers: input registers and DAC registers. The
input registers are connected directly to the input shift register
and the digital code is transferred to the relevant input register
on completion of a valid write sequence. The DAC registers
contain the digital code used by the resistor strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers can change state without affecting the
contents of the DAC registers. When LDAC is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC low when writing to the other DAC input register, all
outputs update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been
updated since the last time LDAC was brought low. Normally,
when LDAC is brought low, the DAC registers are filled with
the contents of the input registers. In the case of the AD5663,
the DAC register updates only if the input register has changed
since the last time the DAC register was updated, thereby
removing unnecessary digital crosstalk.
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Table 12. 24-Bit Input Shift Register Contents of Power-Up/Power-Down Function
MSB
LSB
DB23 to
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
1
0
x
PD1
PD0
x
DAC B
DAC A
Don’t
care
Command bits (C2 to C0)
Address bits (A2 to A0);
don’t care
Don’t
care
Power-down
mode
Don’t care
Power down/Power up
channel selection;
set bit to 1 to select
channel
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