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參數(shù)資料
| 型號： | AD5662BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, 250 ??A, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 357K |
| 代理商： | AD5662BRM |
Preliminary Technical Data
AD5662
MICROPROCESSOR INTERFACING
AD5662 to ADSP-2101/ADSP-2103 Interface
Figure 32 shows a serial interface between the AD5662 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, 24-bit word length.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled.
Rev. PrA | Page 15 of 20
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
DIN
SCLK
0
ADSP-2101/
ADSP-2103*
Figure 32. AD5662 to ADSP-2101/ADSP-2103 Interface
AD5662 to 68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5662 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5662, while the MOSI output drives
the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 should be configured with its CPOL bit as a
0 and its CPHA bit as a 1. When data is being transmitted to the
DAC, the SYNC line is taken low (PC7). When the 68HC11/
68L11 is configured as described above, data appearing on the
MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the AD5662, PC7
is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC; PC7 is taken
high at the end of this procedure.
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
0
68HC11/68L11*
Figure 33. AD5662 to 68HC11/68L11 Interface
AD5662 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5662 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5662,
while RXD drives the serial data line of the part. The SYNC
signal is again derived from a bit programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits
data only in 8-bit bytes; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5662 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TXD
RXD
SYNC
SCLK
DIN
0
Figure 34. AD5662 to 80C51/80L51 Interface
AD5662 to MICROWIRE Interface
Figure 35 shows an interface between the AD5320 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5320 on the rising edge of the SK.
MICROWIRE*
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
0
Figure 35. AD5662 to MICROWIRE Interface
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| AD5662ARJ-2 | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
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