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參數(shù)資料
| 型號(hào)： | AD5662ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, 250 ??A, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 357K |
| 代理商： | AD5662ARM |
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Preliminary Technical Data
AD5662
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Rev. PrA | Page 7 of 20
V
DD
1
V
REF
2
V
FB
3
V
OUT
4
GND
8
DIN
7
SCLK
6
SYNC
5
AD5662
TOP VIEW
(Not to Scale)
0
Figure 3. MSOP/SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
V
DD
2
V
REF
3
V
FB
4
V
OUT
5
SYNC
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V. V
DD
should be decoupled to GND.
Reference Voltage Input.
Feedback Connection for the Output Amplifier.
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24
th
clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Ground Reference Point for All Circuitry on the Part.
6
SCLK
7
DIN
8
GND
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