DATA INPUTS1
參數(shù)資料
型號: AD565AJR
廠商: Analog Devices Inc
文件頁數(shù): 5/12頁
文件大小: 0K
描述: IC DAC 12BIT MONO 250NS 28-SOIC
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設置時間: 250ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 345mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): *
AD565A–SPECIFICATIONS
AD565AJ
AD565AK
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
2.0
5.5
2.0
5.5
V
Bit OFF Logic “0”
0.8
V
Logic Current (Each Bit)
Bit ON Logic “1”
120
300
120
300
A
Bit OFF Logic “0”
35
100
35
100
A
RESOLUTION
12
Bits
OUTPUT
Current
Unipolar (All Bits On)
–1.6
–2.0
–2.4
–1.6
–2.0
–2.4
mA
Bipolar (All Bits On or Off)
0.8
±1.0
1.2
0.8
±1.0
1.2
mA
Resistance (Exclusive of Span Resistors)
6
8
10
6
8
10
k
Offset
Unipolar
0.01
0.05
0.01
0.05
% of F.S. Range
Bipolar (Figure 3, R2 = 50
Fixed)
0.05
0.15
0.05
0.1
% of F.S. Range
Capacitance
25
pF
Compliance Voltage
TMIN to TMAX
–1.5
+10
–1.5
+10
V
ACCURACY (Error Relative to
Full Scale) 25
°C
±1/4
1/2
±1/8
0.35
LSB
(0.006)
(0.012)
(0.003)
(0.0084)
% of F.S. Range
TMIN to TMAX
±1/2
3/4
±1/4
1/2
LSB
(0.012)
(0.018)
(0.006)
(0.012)
% of F.S. Range
DIFFERENTIAL NONLINEARITY
25
°C
±1/2
3/4
±1/4
1/2
LSB
TMIN to TMAX
MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
1
2
1
2
ppm/
°C
Bipolar Zero
5
10
5
10
ppm/
°C
Gain (Full Scale)
15
50
10
20
ppm/
°C
Differential Nonlinearity
2
ppm/
°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
250
400
250
400
ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
15
30
15
30
ns
90% to 10% Delay plus Fall Time
30
50
30
50
ns
TEMPERATURE RANGE
Operating
0
+70
0
+70
°C
Storage
–65
+150
–65
+150
°C
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V dc
3
5
3
5
mA
VEE, –11.4 to –16.5 V dc
–12
–18
–12
–18
mA
POWER SUPPLY GAIN SENSITIVITY
2
VCC = +11.4 to +16.5 V dc
3
10
3
10
ppm of F.S./%
VEE = –11.4 to –16.5 V dc
15
25
15
25
ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
0 to +5
V
–2.5 to +2.5
V
0 to +10
V
–5 to +5
V
–10 to +10
V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50
Resistor for R2 (Figure 2)
±0.1
0.25
±0.1
0.25
% of F.S. Range
Bipolar Zero Error with Fixed
50
Resistor for R1 (Figure 3)
±0.05
0.15
±0.05
±0.1
% of F.S. Range
Gain Adjustment Range (Figure 2)
±0.25
% of F.S. Range
Bipolar Zero Adjustment Range
±0.15
% of F.S. Range
REFERENCE INPUT
Input Impedance
15
20
25
15
20
25
k
REFERENCE OUTPUT
Voltage
9.90
10.00
10.10
9.90
10.00
10.10
V
Current (Available for External Loads)3
1.5
2.5
1.5
2.5
mA
POWER DISSIPATION
225
345
225
345
mW
NOTES
1The digital inputs are guaranteed but not tested over the operating temperature range.
2The power supply gain sensitivity is tested in reference to a V
CC, VEE of
± 15 V dc.
3For operation at elevated temperatures, the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.
(TA = 25 C, VCC = 15 V, VEE = 15 V, unless otherwise noted.)
REV. E
–2–
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