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參數(shù)資料
| 型號： | AD565AJQ |
| 英文描述： | 12-Bit Digital-to-Analog Converter |
| 中文描述： | 12位數(shù)字到模擬轉換器 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 152K |
| 代理商： | AD565AJQ |
AD565A–SPECIFICATIONS
AD565AJ
AD565AK
Typ
Model
DATA INPUTS
1
(Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 3, R2 = 50
Fixed)
Capacitance
Compliance Voltage
T
MIN
to T
MAX
ACCURACY (Error Relative to
Full Scale) +25
°
C
Min
Max
Min
Max
Units
+2.0
+5.5
+0.8
+2.0
+5.5
+0.8
V
V
+120
+35
+300
+100
12
+120
+35
+300
+100
12
μ
A
μ
A
Bits
–1.6
0.8
6
–2.0
±
1.0
8
–2.4
1.2
10
–1.6
0.8
6
–2.0
±
1.0
8
–2.4
1.2
10
mA
mA
k
0.01
0.05
25
0.05
0.15
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
–1.5
+10
–1.5
+10
V
±
1/4
(0.006)
±
1/2
(0.012)
1/2
±
1/8
(0.003)
±
1/4
(0.006)
1/4
LSB
% of F.S. Range
LSB
% of F.S. Range
(0.012)
3/4
(0.018)
(0.006)
1/2
(0.012)
T
MIN
to T
MAX
DIFFERENTIAL NONLINEARITY
+25
°
C
T
MIN
to T
MAX
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
TEMPERATURE RANGE
Operating
Storage
POWER REQUIREMENTS
V
CC
, +11.4 to +16.5 V de
V
EE
, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY
2
V
CC
= +11.4 to +16.5 V dc
V
EE
= –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
±
1/2
3/4
±
1/4
1/2
LSB
MONOTONICITY GUARANTEED
MONOTONICITY GUARANTEED
1
5
15
2
2
10
50
1
5
10
2
2
10
20
ppm/
°
C
ppm/
°
C
ppm/
°
C
ppm/
°
C
250
400
250
400
ns
15
30
30
50
15
30
30
50
ns
ns
0
–65
+70
+150
0
–65
+70
+150
°
C
°
C
3
–12
5
–18
3
–12
5
–18
mA
mA
3
15
10
25
3
15
10
25
ppm of F.S./%
ppm of F.S./%
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
V
V
V
V
V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50
Resistor for R2 (Figure 2)
Bipolar Zero Error with Fixed
50
Resistor for R1 (Figure 3)
Gain Adjustment Range (Figure 2)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (Available for External Loads)
3
POWER DISSIPATION
±
0.1
0.25
±
0.1
0.25
% of F.S. Range
±
0.05
0.15
±
0.05
±
0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
±
0.25
±
0.15
±
0.25
±
0.15
15
20
25
15
20
25
k
9.90
1.5
10.00
2.5
225
10.10
9.90
1.5
10.00
2.5
225
10.10
V
mA
mW
345
345
NOTES
1
The digital inputs are guaranteed but not tested over the operating temperature range.
2
The power supply gain sensitivity is tested in reference to a V
, V
of
±
15 V dc.
3
For operation at elevated temperatures the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.
(T
A
= +25 C, V
CC
= +15 V, V
EE
= +15 V, unless otherwise noted.)
REV. D
–2–
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