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| 型號： | AD5641BKS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, <100 uA, 14-Bit nanoDAC D/A in SC70 Package |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 572K |
| 代理商： | AD5641BKS |
AD5641
Preliminary Technical Data
AD5641 to 68HC11/68L11 Interface
Figure 30 shows a serial interface between the AD5641 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5641, while the MOSI output drives
the serial data line of the DAC. The SYNC signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that its CPOL bit is a 0 and its CPHA
bit is a 1. When data is being transmitted to the DAC, the SYNC
line is taken low (PC7). When the 68HC11/68L11 is configured
as above, data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11/68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the AD5641, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
Rev. PrC | Page 14 of 20
68HC11/
68L11
AD5641*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
PC7
SCK
MOSI
SYNC
SCLK
DIN
0
Figure 30. AD5641 to 68HC11/68L11 Interface
AD5641 to Blackfin ADSP-BF53X Interface
Figure 31 shows a serial interface between the AD5641 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5641, the
setup for the interface is as follows: DT0PRI drives the SDIN
pin of the AD5641, while TSCLK0 drives the SCLK of the part.
The SYNC is driven from TFS0.
ADSP-BF53X
AD5641
*ADDITIONAL PINS OMITTED FOR CLAIRTY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
0
Figure 31. AD5641 to Blackfin ADSP-BF53X Interface
AD5641 to 80C51/80L51 Interface
Figure 32 shows a serial interface between the AD5641 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5641,
while RXD drives the serial data line of the part. The SYNC
signal is again derived from a bit programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmit-
ted to the AD5641, P3.3 is taken low.
The 80C51/80L51 transmits data only in 8-bit bytes; therefore,
only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a
format that has the LSB first. The AD5641 requires its data with
the MSB as the first bit received. The 80C51/80L51 transmit
routine should take this into account.
80C51/80L51*
AD5641*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
P3.3
TXD
RXD
SYNC
SCLK
DIN
0
Figure 32. AD5641 to 80C51/80L51 Interface
AD5641 to MICROWIRE Interface
Figure 33 shows an interface between the AD5641 and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5641 on the rising edge of the SK.
MICROWIRE*
AD5641*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
CS
SK
SO
SYNC
SCLK
DIN
0
Figure 33. AD5641 to MICROWIRE Interface
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