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參數(shù)資料
| 型號(hào)： | AD5640 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行DAC |
| 英文描述： | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
| 中文描述： | 單，12-/14-/16-Bit 5分之/ C對芯片參考采用SOT - 23 nanoDAC系列 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 558K |
| 代理商： | AD5640 |
AD5620/AD5640/AD5660
of the AD8627 and possible latch-up of the controller. The loop
supply voltage compliance of the circuit is limited by the maximum
applied input voltage to the ADR02 and is from 12 V to 40 V.
Rev. A | Page 22 of 24
0
SLOAD
AD5660
V
12V TO 36V
4–20mA
AD8627
R1
4.7k
Ω
R2
18.5k
Ω
A2P1
P2
AD4mA
R6
3.3k
Ω
R3
1.5k
Ω
D1
Q1
R7
100
Ω
RL
ADR02
Figure 51. Programmable 4 to 20 mA Process Controller
USING THE AD5620/AD5640/AD5660 WITH A
GALVANICALLY ISOLATED INTERFACE
For process-control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. The
i
Coupler provides isolation in
excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire
serial logic interface; therefore, the ADuM1300 3-channel
digital isolator provides the required isolation (see Figure 52).
The power supply to the part also must be isolated, which is
done by using a transformer. On the DAC side of the trans-
former, a 5 V regulator provides the 5 V supply required for the
AD5620/AD5640/AD5660.
0.1
μ
F
5V
REGULATOR
GND
0
DIN
SYNC
SCLK
POWER
10
μ
F
SDI
SCLK
DATA
AD56x0
V
OUT
VOB
VOA
VOC
V
DD
V1C
V1B
V1A
ADuM1300
Figure 52. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5620/
AD5640/AD5660 should have separate analog and digital
sections, each having its own area of the board. If the AD5620/
AD5640/AD5660 are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5620/AD5640/AD5660.
The power supply to the AD5620/AD5640/AD5660 should be
bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should be as close as physically possible to the device, with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor has a low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 μF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other components with
fast switching digital signals should be shielded from other
parts of the board by digital ground. Avoid crossover of digital
and analog signals if possible. When traces cross on opposite
sides of the board, ensure that they run at right angles to each
other to reduce feedthrough effects on the board. The best
board layout technique is the microstrip technique, where the
component side of the board is dedicated to the ground plane
only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
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