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參數(shù)資料
| 型號： | AD5620CRM-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 558K |
| 代理商： | AD5620CRM-3 |
AD5620/AD5640/AD5660
INPUT SHIFT REGISTER
AD5620/AD5640
The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 40 and Figure 41). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16th falling edge of SCLK.
Rev. A | Page 18 of 24
AD5660
The input shift register is 24 bits wide for the AD5660 (see
Figure 42). The first six bits are don’t care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence for the AD5660, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs—see Figure 43.
Similarly, in a normal write sequence for the AD5620/AD5640,
the SYNC line is kept low for at least 16 falling edges of SCLK,
and the DAC is updated on the 16th falling edge. However, if
SYNC is brought high before the 16th falling edge, this acts as
an interrupt to the write sequence.
DATA BITS
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
Figure 40. AD5620 Input Register Contents
DATA BITS
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D11
D10
D13
D12
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Figure 41. AD5640 Input Register Contents
DATA BITS
DB23 (MSB)
DB0 (LSB)
PD1
PD0
D15
D14
D13
D12
X
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Figure 42. AD5660 Input Register Contents
0
DIN
MSB
MSB
LSB
LSB
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
/24
TH
FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
/24
TH
FALLING EDGE
SYNC
SCLK
Figure 43. SYNC Interrupt Facility
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