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參數(shù)資料
| 型號(hào)： | AD5620BRJ-2500RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | MO-178BA, SOT-23, 8 PIN |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 558K |
| 代理商： | AD5620BRJ-2500RL7 |
AD5620/AD5640/AD5660
SPECIFICATIONS
AD5620/AD5640/AD5660-2-3
V
DD
= 4.5 V to 5.5 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND, C
REFOUT
= 100 nF; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
A Grade
1
B Grade
1
C Grade
1
STATIC PERFORMANCE
2
AD5660
Resolution
16
16
16
Relative Accuracy
±32
±16
±16
Differential Nonlinearity
±1
±1
±1
AD5640
Resolution
14
14
14
Relative Accuracy
±8
±4
±4
Differential Nonlinearity
±1
±1
±1
AD5620
Resolution
12
12
12
Relative Accuracy
±6
±1
±1
Differential Nonlinearity
±1
±1
±1
Zero-Code Error
2
2
2
10
10
10
Offset Error
±10
±10
±10
Full-Scale Error
0.15
0.15
0.15
1
1
1
Gain Error
±1.5
±1.5
±1.5
Zero-Code Error Drift
±2
±2
±2
Gain Temperature Coefficient
±2.5
±2.5
±2.5
DC Power Supply Rejection Ratio
75
75
75
OUTPUT CHARACTERISTICS
3
Output Voltage Range
0
0
0
V
DD
V
DD
V
DD
Output Voltage Settling Time
8
8
8
10
10
10
Slew Rate
1.5
1.5
1.5
Capacitive Load Stability
2
2
2
10
10
10
Output Noise Spectral Density
80
80
80
Output Noise (0.1 Hz to 10 Hz)
45
45
45
Digital-to-Analog Glitch Impulse
5
5
5
Digital Feedthrough
0.1
0.1
0.1
DC Output Impedance
0.5
0.5
0.5
Short-Circuit Current
30
30
30
Power-Up Time
5
5
5
REFERENCE OUTPUT
Output Voltage
2.495
2.495
2.495
2.505
2.505
2.505
Reference TC
3
±10
±10
±5
±20
Output Impedance
2.8
2.8
2.8
Rev. A | Page 3 of 24
Unit
Bits min
LSB max
LSB max
Bits min
LSB max
LSB max
Bits min
LSB max
LSB max
mV typ
mV max
mV max
% FSR typ
% FSR max
% FSR max
μV/°C typ
ppm typ
dB typ
V min
V max
μs typ
μs max
V/μs typ
nF typ
nF typ
nV/√Hz typ
μV p-p typ
nV-s typ
nV-s typ
Ω typ
mA typ
μs typ
V min
V max
ppm/°C typ
ppm/°C max
kΩ typ
Conditions/Comments
Guaranteed monotonic by design
Guaranteed monotonic by design
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; V
DD
= 5 V ± 10%
to scale change settling to ±2 LSB
R
L
= 2 kΩ; 0 pF < C
L
< 200 pF
to scale
R
L
= ∞
R
L
= 2 kΩ
DAC code = midscale, 10 kHz
DAC code = midscale
1 LSB change around major carry
V
DD
= 5 V
Coming out of power-down mode; V
DD
= 5 V
At ambient
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