參數(shù)資料
型號(hào): AD5611BKS
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
中文描述: SERIAL INPUT LOADING, 8 us SETTLING TIME, 10-BIT DAC, PDSO6
封裝: PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6
文件頁數(shù): 5/20頁
文件大?。?/td> 599K
代理商: AD5611BKS
Preliminary Technical Data
AD5601/AD5611/AD5621
Parameter
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= ±4.5 V to ±5.5 V
V
DD
= ±2.7 V to ±3.6 V
I
DD
(All Power-Down Modes)
V
DD
= ±4.5 V to ±5.5 V
V
DD
= ±2.7 V to ±3.6 V
POWER EFFICIENCY
I
OUT
/I
DD
Rev. PrC | Page 5 of 20
B Version
1
Typ
0.2
0.05
TBD
Unit
V
μA
μA
μA
μA
%
Test Conditions/Comments
All digital inputs at 0 or V
DD
DAC active and excluding load current
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
I
LOAD
= 2 mA and V
DD
= ±5 V
Min
2.7
Max
5.5
100
70
1
1
1
Temperature ranges are as follows: B Version: –40°C to +125°C, typical at +25°C.
2
Linearity calculated using a reduced code range.
3
Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 2.
Table 3.
Parameter
Limit
1
Unit
t
12
33
ns min
t
2
13
ns min
t
3
12
ns min
t
4
13
ns min
t
5
5
ns min
t
6
4.5
ns min
t
7
0
ns min
t
8
33
ns min
t
9
13
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0
D1
D2
D14
D15
DIN
SYNC
SCLK
0
t
9
t
1
t
8
D15
D14
Figure 2. Timing Diagram
相關(guān)PDF資料
PDF描述
AD5621BKS 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
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