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參數(shù)資料
| 型號： | AD5582YRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO48 |
| 封裝： | 1.10 MM HEIGHT, TSSOP-48 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 162K |
| 代理商： | AD5582YRU-REEL7 |
ELECTRICAL CHARACTERISTICS
at V
DD
=+5V, V
SS
= -5V, V
L
= +5V±10%, VREFH = +2.5V, VREFL = -2.5V, -40°C < TA < +125°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITION
STATIC PERFORMANCE
Resolution
1
N
AD5582
Resolution
1
N
AD5583
Relative Accuracy
2
INL
Differential Nonlinearity
2
DNL
Monotonic
Zero-Scale Error
VZSE
Data = 000H
Full-Scale Voltage Error
VFSE
Data = FFFH
Full-Scale Tempco
3
TCVFS
REFERENCE INPUT
VREFH Input Range
4
VREFH
VREFL Input Range
4
VREFL
Input Resistance
8
RREF
Data = 555
H
Input Capacitance
3
CREF
REF Input Current
IREF
REF Multiplying Bandwidth
BWREF
ANALOG OUTPUT
Output Current
IOUT
Data = 800H,
VOUT = 4LSB
Capacitive Load
3
CL
No Oscillation
LOGIC INPUTS
Logic Input Low Voltage
VIL
V
L
= 5V ± 10%
Logic Input High Voltage
VIH
V
L
= 5V ± 10%
Input Leakage Current
IIL
Input Capacitance
3
CIL
Output Voltage High
V
OH
I
OH
= -0.8mA
Output Voltage Low
V
OL
I
OL
= 1.6mA
AC CHARACTERISTICS
Output Slew Rate
SR
Data = 000H to FFFH to 000H
Settling Time
7
tS
To ±0.1% of Full Scale
Shutdown Recovery
t
SDR
DAC Glitch
Q
Code 7FF
H
to 800
H
to 7FF
H
Digital Feed Through
VOUT/t
CS
Data=800
H
,
CS
toggles at f=16MHz
Analog Crosstalk
VOUT/VREF
Output Noise
e
N
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIL = 0V, No Load
Negative Supply Current
ISS
VIL = 0V, No Load
Power Dissipation
PDISS
VIL = 0V, No Load
Power Supply Sensitivity
PSS
VDD = ±5%
NOTES:
1.
DAC Output Equation: V
OUT
= V
REFL
+ [(V
REFH
-V
REFL
)*Code/2^N], where Code = data loaded in corresponding DAC register A, B, C, D and N equals the
DAC resolution AD5582 = 12, AD5583 = 10 bits. One LSB = VREF/4096V for the 12-bit AD5582.
2.
The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.
3.
These parameters are guaranteed by design and not subject to production testing.
4.
When V
REF
is connected to either the V
DD
or the V
SS
power supply the corresponding V
OUT
voltage will program between ground and the supply voltage
minus the offset voltage of the output buffer, which is the same as the V
ZSE
error specification. See additional discussion in the operation section of the data
sheet.
5.
Typical specifications represent average readings measured at 25°C.
6.
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
2
MIN
TYP
MAX
UNITS
12
10
10
Bits
Bits
LSB
LSB
LSB
LSB
ppm/
o
C
-1
-1
+1
2
2
V
SS
V
SS
10
V
DD
V
DD
500
V
V
K
5
pF
μ
A
Hz
80
±2
mA
pF
500
0.8
0.4
V
V
μ
A
pF
V
V
2.4
2.4
2
5
V/
μ
s
μ
s
μ
s
nVs
nVs
dB
nV
√
Hz
100
5
-80
40
VREF = 1.5V
DC
+1VP-P, Data = 000H, f=100KHz
3
3
30
mA
mA
mW
ppm/V
30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5582YRV | 制造商:Analog Devices 功能描述:QUAD 12BIT DAC SMD 5582 TSSOP48 |
| AD5582YRVZ | 功能描述:IC DAC 12BIT QUAD VOUT 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD5582YRVZ | 制造商:Analog Devices 功能描述:QUAD 12BIT DAC SMD 5582 TSSOP48 |
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| AD5583 | 制造商:AD 制造商全稱:Analog Devices 功能描述:QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter |
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