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參數資料
| 型號： | AD557JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | DACPORT, Low-Cost Complete mP-Compatible 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 8-BIT DAC, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數： | 2/4頁 |
| 文件大小： | 238K |
| 代理商： | AD557JP |
AD557–SPECIFICATIONS
Model
Min
Typ
Max
Units
RESOLUTION
8
Bits
RELATIVE ACCURACY
0 to + 70
°
C
OUTPUT
Ranges
Current Source
Sink
±
1/2
1
LSB
0 to + 2.56
V
mA
+5
Internal Passive
Pull-Down to Ground
2
OUTPUT SETTLING TIME
3
FULL-SCALE ACCURACY
4
@ +25
°
C
T
MIN
to T
MAX
ZERO ERROR
@ +25
°
C
T
MIN
to T
MAX
MONOTONICITY
5
T
MIN
to T
MAX
DIGITAL INPUTS
T
to T
Input Current
Data Inputs, Voltage
Bit On—Logic “1”
Bit On—Logic “0”
Control Inputs, Voltage
On—Logic “1”
On—Logic “0”
Input Capacitance
TIMING
6
t
W
Strobe Pulse Width
T
to T
t
DH
Data Hold Time
T
to T
t
DS
Data Setup Time
T
MIN
to T
MAX
POWER SUPPLY
Operating Voltage Range (V
CC
)
2.56 Volt Range
Current (I
)
Rejection Ratio
0.8
1.5
μ
s
±
1.5
±
2.5
±
2.5
±
4.0
LSB
LSB
±
1
±
3
LSB
LSB
Guaranteed
6
100
μ
A
2.0
0
V
V
0.8
2.0
0
V
V
pF
0.8
4
225
300
10
10
225
300
ns
ns
ns
ns
ns
ns
+4.5
+5.5
25
0.03
V
mA
%/%
15
POWER DISSIPATION, V
CC
= 5 V
OPERATING TEMPERATURE RANGE
75
125
mW
°
C
0
+70
NOTES
1
Relative Accuracy is defined as the deviation of the code transition points from the
ideal transfer point on a straight line from the zero the the full scale of the device.
2
Passive pull-down resistance is 2 k
.
3
Settling time is specified for a positive-going full-scale step to
±
1/2 LSB. Negative-
going steps to zero are slower, but can be improved with an external pull-down.
4
The full-scale output voltage is 2.55 V and is guaranteed with a +5 V supply.
5
A monotonic converter has a maximum differential lineraity error of
±
1 LSB.
6
See Figure 7.
Specifications subject to change without notice.
(@ T
A
= +25
8
C, V
CC
= +5 V unless otherwise noted)
PIN CONFIGURATIONS
DIP
10
9
13
12
11
16
15
14
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD557
LSB BIT 8
GND
V
OUT
SENSE B
V
OUT
SENSE A
V
OUT
BIT 7
BIT 6
BIT 5
CS
+V
CC
GND
BIT 4
BIT 3
BIT 2
MSB BIT 1
CE
PLCC
N
20 19
18
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
BIT 6
BIT 5
NC
BIT 4
BIT 3
V
OUT
SENSE B
GND
NC
GND
+V
CC
NC = NO CONNECT
AD557
B
B
N
V
O
V
O
B
(
C
C
ABSOLUTE MAXIMUM RATINGS
*
V
CC
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . .0 V to +7.0 V
V
OUT
. . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground
Momentary Short to V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 mW
Storage Temperature Range
N/P (Plastic) Packages . . . . . . . . . . . . . . . .–25
°
C to +100
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . 300
°
C
Thermal Resistance
Junction to Ambient/Junction to Case
N/P (Plastic) Packages . . . . . . . . . . . . . . . . . .140/55
°
C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
REV. A
–2–
ORDERING GUIDE
Model
Temperature Range
Package Option*
AD557JN
AD557JP
0
°
C to +70
°
C
0
°
C to +70
°
C
N-16
P-20A
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
CIRCUIT DESCRIPTION
The AD557 consists of four major functional blocks fabricated
on a single monolithic chip (see Figure 1). The main D/A con-
verter section uses eight equally weighted laser-trimmed current
sources switched into a silicon-chromium thin-film R/2R resistor
ladder network to give a direct but unbuffered 0 mV to 400mV
output range. The transistors that form the DAC switches are
PNPs; this allows direct positive-voltage logic interface and a
zero-based output range.
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