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參數(shù)資料
| 型號(hào)： | AD557JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | DACPORT, Low-Cost Complete mP-Compatible 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 4/4頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | AD557JN |
AD557
REV. A
–4–
P
two commons could develop. To protect devices that interface
to both digital and analog parts of the system, such as the
AD557, it is recommended that common ground tie-points
should be provided at
each
such device. If only one system
ground can be connected directly to the AD557, it is recom-
mended that analog common be selected.
Figure 4. Recommended Grounding and Bypassing
USING A “FALSE” GROUND
Many applications, such as disk drives, require servo control
voltages that swing on either side of a “false” ground. This
ground is usually created by dividing the +12 V supply equally
and calling the midpoint voltage “ground.”
Figure 5 shows an easy and inexpensive way to implement this.
The AD586 is used to provide a stable 5 V reference from the
system’s +12 V supply. The op amp shown likewise operates
from a single (+12 V) supply available in the system. The result-
ing output at the V
OUT
node is
±
2.5 V around the “false”
ground point of 5 V. AD557 input code vs. V
OUT
is shown in
Figure 6.
Figure 5. Level Shifting the AD557 Output Around a
“False” Ground
TIMING AND CONTROL
The AD557 has data input latches that simplify interface to 8-
and 16-bit data buses. These latches are controlled by Chip
Enable (
CE
) and Chip Select (
CS
) inputs.
CE
and
CS
are inter-
nally “NORed” so that the latches transmit input data to the
DAC section when both
CE
and
CS
are at Logic “0”. If the
application does not involve a data bus, a “00” condition allows
for direct operation of the DAC. When either
CE
or
CS
go to
Logic “1,” the input data is latched into the registers and held
until both
CE
and
CS
return to “0.” (Unused
CE
or
CS
inputs
should be tied to ground.) The truth table is given in Table I.
The logic function is also shown in Figure 6.
Figure 6. AD557 Input Code vs. Level Shifted Output in a
“False” Ground Configuration
Table I. AD557 Control Logic Truth Table
Latch
Condition
Input Data
CE
CS
DAC Data
0
1
0
1
0
1
X
X
0
0
g
g
0
0
1
X
0
0
0
0
g
g
X
1
0
1
0
1
0
1
previous data
previous data
“transparent”
“transparent”
latching
latching
latching
latching
latched
latched
NOTES
X = Does not matter
g
= Logic Threshold at Positive-Going Transition
In a level-triggered latch such as that used in the AD557, there
is an interaction between the data setup and hold times and the
width of the enable pulse. In an effort to reduce the time
required to test all possible combinations in production, the
AD557 is tested with T
DS
= T
W
= 225 ns at 25
°
C and 300 ns at
T
MIN
and T
MAX
, with T
DH
= 10 ns at all temperatures. Failure
to comply with these specifications may result in data not being
latched properly.
Figure 7 shows the timing for the data and control signals,
CE
and
CS
are identical in timing as well as in function.
Figure 7. AD557 Timing
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N (Plastic) Package
P (PLCC) Package
C
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