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| 型號： | AD5570YRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封裝： | PLASTIC, MO-150AC, SSOP-16 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 963K |
| 代理商： | AD5570YRS |
AD5570
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 24
V
SS
V
DD
CLR
1
2
3
LDAC
4
SYNC
5
SCLK
6
SDIN
7
SDO
8
REFGND
REFIN
REFGND
V
OUT
AGNDS
16
15
14
13
12
AGND
PD
DGND
11
10
9
AD5570
TOP VIEW
(Not to Scale)
0
Figure 5. 16-Lead SSOP Pin Configuration (RS-16)
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
V
SS
2
V
DD
3
CLR
Description
Negative Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
Positive Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
Level Sensitive, Active Low Input. A falling edge of CLR resets V
OUT
to AGND. The contents of the registers are
untouched.
Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC may be tied
permanently low, enabling the outputs to be updated on the rising edge of SYNC.
Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers
on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of
the following 16 clocks.
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 8 MHz.
Serial Data Input. This device has a 16-bit register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Data Output. Can be used for daisy chaining a number of devices together or for reading back the data in
the shift register for diagnostic purposes. This is an open-drain output; it should be pulled to logic high with an
external pull-up resistor of ~5 k.
Digital Ground. Ground reference for all digital circuitry.
Active Low Control Input. Allows the DAC to be put into a power-down state.
Analog Ground. Ground reference for all analog circuitry.
Analog Ground Sense. This is normally tied to AGND.
Analog Output Voltage.
This pin should be tied to 0 V.
Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar ±10 V output
range, REFIN is 5 V.
This pin should be tied to 0 V.
4
LDAC
5
SYNC
6
SCLK
7
SDIN
8
SDO
9
10
11
12
13
14
15
DGND
PD
AGND
AGNDS
V
OUT
REFGND
REFIN
16
REFGND
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