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參數(shù)資料
| 型號： | AD5570ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封裝： | PLASTIC, MO-150AC, SSOP-16 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 963K |
| 代理商： | AD5570ARS |
AD5570
GENERAL DESCRIPTION
The AD5570 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of ±11.4 V to ±16.5 V, and has a
buffered voltage output of up to ±13.6 V. Data is written to the
AD5570 in a 16-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy
chaining or readback.
Rev. 0 | Page 16 of 24
The AD5570 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V. The device also
has a power-down pin, which reduces the typical current
consumption to 16 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit
current-mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 35.
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
the 15 matched resistors to either AGND or IOUT. The remain-
ing 12 bits of the data word drive switches S0 to S11 of the
12-bit R-2R ladder network.
2R
E15
Vref
2R
E14
E1
2R
S11
R
R
R
2R
S10
2R
12 BIT R-2R LADDER
V
OUT
2R
S0
2R
AGND
R/8
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
0
Figure 35. DAC Ladder Structure
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference
input (REFIN) has an input range of up to 7 V. This input
voltage is then used to provide a buffered positive and negative
reference for the DAC core. The positive reference is given by
REFIN
REF
V
2
V
×
=
+
while the negative reference to the DAC core is given by
REFIN
V
REF
2
V
×
=
These positive and negative reference voltages define the DAC
output range.
SERIAL INTERFACE
The AD5570 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 10 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 2.
Upon power-up, the input shift register and DAC register are
loaded with midscale (0x8000). The DAC coding is straight
binary; all 0s produce an output of 2 V
REF
; all 1s produce an
output of +2 V
REF
1 LSB.
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. SYNC must frame the
serial word being loaded into the device. Data can be trans-
ferred into the device only while SYNC is low. To start the serial
data transfer, SYNC should be taken low, observing the
minimum SYNC to SCLK falling edge setup time, t
4
. After
SYNC goes low, serial data on SDIN is shifted into the device’s
input shift register on the falling edges of SCLK. SYNC may be
taken high after the falling edge of the 16th SCLK pulse,
observing the minimum SCLK falling edge to SYNC rising edge
time, t
7
.
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register of
the DAC.
When data has been transferred into the input register of the
DAC, the DAC register and DAC output can be updated by
taking LDAC low while SYNC is high.
Load DAC Input (LDAC)
When data has been transferred into the input register of the
DAC, there are two ways in which the DAC register and DAC
output can be updated. Depending on the status of both SYNC
and LDAC, one of two update modes is selected.
Synchronous LDAC:
In this mode, LDAC is low while data is
being clocked into the input shift register. The DAC output is
updated when SYNC is taken high. The update here occurs on
the rising edge of SYNC.
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| AD5570ARS-REEL | 功能描述:IC DAC 16BIT SRL IN/VOUT 16-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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| AD5570ARSZ | 功能描述:IC DAC 16BIT SERIAL IN 16SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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