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參數(shù)資料
| 型號： | AD5553CRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| 中文描述： | SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO8 |
| 封裝： | 3 X 4.70 MM, MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 259K |
| 代理商： | AD5553CRM |
REV. A
AD5543/AD5553
–7–
CIRCUIT OPERATION
The AD5543/AD5553 contains a 16-/14-bit, current output,
digital-to-analog converter, a serial input register, and a DAC
register. Both converters use a 3-wire serial data interface.
D/A Converter Section
The DAC architecture uses a current steering R-2R ladder
design. Figure 4 shows the typical equivalent DAC structure.
The DAC contains a matching feedback resistor for use with an
external op amp, (see Figure 5). With R
FB
and I
OUT
terminals
connected to the op amp output and inverting node respec-
tively, a precision voltage output can be achieved as:
V
V
D
OUT
REF
=
×
–
/
,
65 536
V
V
D
OUT
REF
=
×
–
/
,
16 384
Note that the output voltage polarity is opposite to the
V
REF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The V
DD
power pin is only used by
the internal logic to drive the DAC switches
’
ON and OFF states.
AD
(
)
5543
(1)
AD
(
)
5553
(2)
V
REF
V
DD
R
FB
I
OUT
R
R
R
GND
2R
2R
2R
R
5k
S1
S2
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;
SWITCHES S1 AND S2 ARE CLOSED, V
DD
MUST BE POWERED
Figure 4. Equivalent R-2R DAC Circuit
Note that a matching switch is used in series with the internal 5 k
feedback resistor. If users attempt to measure RFB, power must be
applied to V
DD
to achieve continuity.
V
DD
V
REF
V
REF
V
DD
U2
U1
AD5543/AD5553
–5V
V
O
GND
I
OUT
V+
V–
R
FB
AD8628
Figure 5. Voltage Output Configuration
These DACs are also designed to accommodate ac reference
input signals. The AD5543 accommodates input reference
voltages in the range of
–
12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input resistance value of 5 k
,
±
30%. The DAC output (I
OUT
) is code-dependent, producing
various resistances and capacitances. External amplifier choice
should take into account the variation in impedance generated
by the AD5543 on the amplifier
’
s inverting input node. The
feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. To maintain good analog perfor-
mance, power supply bypassing of 0.01
μ
F to 0.1
μ
F ceramic or
chip capacitors in parallel with a 1
μ
F tantalum capacitor is recom-
mended. Due to degradation of power supply rejection ratio in
frequency, users must avoid using switching power supplies.
SERIAL DATA INTERFACE
The AD5543/AD5553 uses a 3-wire (
CS
, SDI, CLK) serial
data interface. New serial data is clocked into the serial input
register in a 16-bit data-word format for AD5543. The MSB is
loaded first. Table II defines the 16 data-word bits. Data is
placed on the SDI pin and clocked into the register on the positive
clock
edge of CLK, subject to the data setup and hold time
requirements specified in the interface timing specifications
.
Only the last 16 bits clocked into the serial register are inter-
rogated when the
CS
pin is strobed to transfer the serial register
data to the DAC register. Since most microcontrollers output
serial data in 8-bit bytes, two data bytes can be written to the
AD5543/AD5553. After loading the serial register, the rising edge
of
CS
transfers the serial register data to the DAC register;
during this strobe, the CLK should not be toggled. For the
AD5553, with 16-bit clock cycles, the two LSBs are ignored.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zener
diodes connected to ground (GND) and V
DD
as shown in Figure 6.
V
DD
DIGITAL
INPUTS
5k
DGND
Figure 6. Equivalent ESD Protection Circuits
PCB Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
It is also essential to bypass the power supplies with quality
capacitors for optimum stability. Supply leads to the device should
be bypassed with 0.01
μ
F to 0.1
μ
F disc or chip ceramic capaci-
tors. Low-ESR 1
μ
F to 10
μ
F tantalum or electrolytic capacitors
should also be applied at the supplies to minimize transient
disturbance and filter out low frequency ripple
The PCB metal traces between V
REF
and R
FB
should also be
matched to minimize gain error.
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