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參數(shù)資料
| 型號(hào)： | AD5552BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | 5 V, Serial-Input Voltage-Output, 14-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | AD5552BR |
AD5551/AD5552
–10–
REV. 0
Force Sense Buffer Amplifier Selection
These amplifiers can be single-supply or dual supplies, low-
noise amplifiers. A low-output impedance at high frequencies
is preferred as they need to be able to handle dynamic currents
of up to
±
20 mA.
Reference and Ground
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5551/
AD5552 operates with a voltage reference ranging from 2V to
V
DD
. Although DAC’s full-scale output voltage is determined
by the reference, references below 2 V will result in reduced
accuracy. Tables I and II outline the analog output voltage
for particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5552.
If the application does not require separate force and sense lines,
they should be tied together close to the package to minimize
voltage drops between the package leads and the internal die.
ADR291 and ADR293 are suitable references for this product.
Power-On Reset
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. On power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 14 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 14 bits are loaded,
only the last 14 are kept, and if fewer than 14 are loaded, bits
will remain from the previous word. If the AD5551/AD5552
needs to be interfaced with data shorter than 14 bits, the data
should be padded with zeros at the LSBs.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that
the reference and supply pins be bypassed with a 10
μ
F tantalum
capacitor in parallel with a 0.1
μ
F ceramic capacitor.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5551/AD5552 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5551/AD5552
requires a 14-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5552 only).
ADSP-2101/ADSP-2103 to AD5551/AD5552 Interface
Figure 5 shows a serial interface between the AD5551/AD5552
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set to operate in the SPORT (Serial Port) transmit
alternate framing mode. The ADSP-2101/ADSP-2103 is pro-
grammed through the SPORT control register and should be
configured as follows: Internal Clock Operation, Active Low
Framing, 16-Bit Word Length. The first 2 bits are DON’T CARE
as AD5551/AD5552 will keep the last 14 bits. Transmission is
initiated by writing a word to the Tx register after the SPORT has
been enabled. Because of the edges-triggered difference, an inverter
is required at the SCLKs between the DSP and the DAC.
SCLK
DIN
CS
TFS
DT
SCLK
ADSP-2101/
ADSP-2103
*
*
ADDITIONAL PINS OMITTED FOR CLARITY.
**
AD5552 ONLY
AD5551/
AD5552
*
LDAC
**
FO
Figure 5. ADSP-2101/ADSP-2103 to AD5551/AD5552
Interface
68HC11 to AD5551/AD5552 Interface
Figure 6 shows a serial interface between the AD5551/AD5552
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the SCLK of the DAC, while the MOSI output drives the
serial data lines SDIN.
CS
signal is driven from one of the
port lines. The 68HC11 is configured for master mode; MSTR
= 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI
output is valid on the rising edge of SCK.
PC7
MOSI
SCK
68HC11/
68L11
*
PC6
SCLK
DIN
CS
*
ADDITIONAL PINS OMITTED FOR CLARITY.
**
AD5552 ONLY
AD5551/
AD5552
*
LDAC
**
Figure 6. 68HC11/68L11 to AD5551/AD5552 Interface
MICROWIRE to AD5551/AD5552 Interface
Figure 7 shows an interface between the AD5551/AD5552 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5551/
AD5552 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
MICROWIRE
*
CS
SO
SCLK
DIN
CS
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5551/
AD5552
*
Figure 7. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 to AD5551/AD5552 Interface
A serial interface between the AD5551/AD5552 and the 80C51/
80L51 microcontroller is shown in Figure 8. TxD of the
microcontroller drives the SCLK of the AD5551/AD5552, while
RxD drives the serial data line of the DAC. P3.3 is a bit program-
mable pin on the serial port which is used to drive
CS
.
P3.3
RxD
TxD
80C51/
80L51
*
P3.4
SCLK
DIN
CS
*
ADDITIONAL PINS OMITTED FOR CLARITY.
**
AD5552 ONLY
AD5551/
AD5552
*
LDAC
**
Figure 8. 80C51/80L51 to AD5551/AD5552 Interface
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