參數(shù)資料
型號: AD5543BRZ
廠商: Analog Devices Inc
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: IC DAC 16BIT SRLIN/CUR OUT 8SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 500ns
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
產(chǎn)品目錄頁面: 783 (CN2011-ZH PDF)
AD5543/AD5553
Data Sheet
Rev. F | Page 4 of 20
Parameter
Symbol
Condition
5 V ± 10%
Unit
AC CHARACTERISTICS4
Output Voltage Settling Time
tS
To ±0.1% of full scale,
0.5
s typ
Data = 0x0000 to 0xFFFF to 0x0000 for AD5543
Data = 0x0000 to 0x3FFF to 0x0000 for AD5553
Reference Multiplying Bandwidth
BW
VREF = 100 mV rms, data = 0xFFFF
6.6
MHz typ
DAC Glitch Impulse
Q
VREF = 0 V, data = 0x7FFF to 0x8000 for AD5543
7
nV-sec
Feedthrough Error
VOUT/VREF
Data = 0x0000, VREF = 100 mV rms, same channel
83
dB
Digital Feedthrough
Q
CS = 1 and fCLK = 1 MHz
7
nV-sec
Total Harmonic Distortion
THD
VREF = 5 V p-p, data = 0xFFFF, f = 1 kHz
103
dB typ
Output Spot Noise Voltage
eN
f = 1 kHz, BW = 1 Hz
12
nV/√Hz
1
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is
tied to the amplifier output. The +IN op amp is grounded, and the DAC IOUT is tied to the IN op amp. Typical values represent average readings measured at 25°C.
2
These parameters are guaranteed by design and are not subject to production testing.
3
All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.
4
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
TIMING DIAGRAMS
SDI
CLK
CS
tCSH
tCSS
tDS
tDH
tCH
tCL
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
02917-
016
Figure 4. AD5543 Timing Diagram
tCSH
tCSS
tDS
tDH
tCH
tCL
SDI
CLK
CS
D13
D12
D11
D10
D9
D8
D7
D6
D1
D0
02917-
017
Figure 5. AD5553 Timing Diagram
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