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參數(shù)資料
| 型號： | AD5542CR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 5 V, Serial-Input Voltage-Output, 16-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PDSO14 |
| 封裝： | MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 186K |
| 代理商： | AD5542CR |
AD5541/AD5542
–3–
REV. A
SCLK
CS
DIN
DB15
LDAC
*
DB0
t
1
*AD5542
ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t
2
t
3
t
5
t
6
t
7
t
8
t
9
t
11
t
4
t
10
t
12
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
1,
2
Limit at T
MIN
, T
MAX
All Versions
Parameter
Unit
Description
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
25
40
20
20
15
15
35
20
15
0
30
30
30
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS
Low to SCLK High Setup
CS
High to SCLK High Setup
SCLK High to
CS
Low Hold Time
SCLK High to
CS
High Hold Time
Data Setup Time
Data Hold Time
LDAC
Pulsewidth
CS
High to
LDAC
Low Setup
CS
High Time Between Active Periods
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5ns (10% to
90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
(V
DD
= 5 V
6
5%, V
REF
= 2.5 V, AGND = DGND = 0 V. All specifications T
A
= T
MIN
to T
MAX,
unless
otherwise noted.)
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