參數(shù)資料
型號(hào): AD5539
廠商: Analog Devices, Inc.
英文描述: Ultrahigh Frequency Operational Amplifier(超高頻率運(yùn)算放大器)
中文描述: 超高頻率運(yùn)算放大器(超高頻率運(yùn)算放大器)
文件頁數(shù): 13/16頁
文件大?。?/td> 499K
代理商: AD5539
AD5539
–13–
REV. B
APPLICAT IONS SUMMARY CHART
GAIN
FLAT NE SS
(T RIMME D)
3 dB
R1
R2
1
R
LAG
C
LAG2
C
LE AD2
GAIN
BANDWIDT H
Gain = –1 to –5
Circuit of Fig. 17
R
2
G
2 k
R
1
4
R
1
R
2±1
1
2
π
44
×
10
6
(
)
R
LAG
3
pF
G
–2
±
0.2 dB
200 MHz
Gain = –1 to –5
Circuit of Fig. 23
R
2
G
2 k
R
1
4
R
1
R
2±1
1
2
π
44
×
10
6
(
)
R
LAG
3
pF
G
–2
±
1 dB
180 MHz
Gain = +2 to +5
3
Circuit of Fig. 27
R
2
G
±1
2 k
R
1
10
R
1
R
2
±1
1
2
π
44
×
10
6
(
)
R
LAG
3
pF
G
±1
+3
±
1 dB
390 MHz
Gain = +2 to +5
4
Circuit of Fig. 29
R
2
G
±1
2 k
R
1
10
R
1
R
2
±1
NA
3
pF
G
±1
+3
±
0.5 dB
340 MHz
Gain < –5
R
2
G
1.5 k
NA
NA
T rimmer
5
–20
±
0.2 dB
80 MHz
Gain > +5
R
2
G
±1
1.5 k
NA
NA
T rimmer
5
+20
±
0.2 dB
80 MHz
NOT ES
G = Gain
1
Values given for specific results summarized here—applications can be adapted for values different than those specified.
2
It is recommended that C
LEAD
and C
LAG
be trimmers covering a range that includes the computed value above.
3
R
SOURCE
200
.
4
R
50
.
5
Use Voltronics CPA2 0.1–2.5 pF T eflon T rimmer Capacitor (or equivalent).
NA = Not Applicable
T he photos of Figures 40 and 41 demonstrate how the AD5539
easily settles to 1% (1 mV) in less than 12 ns; settling to 0.1%
(100
μ
V) requires less than 25 ns.
Figure 40. Error Signal from AD5539 Settling Time Test
Circuit – Falling Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500
μ
V/div
Figure 41. Error Signal from AD5539 Settling Time Test
Circuit – Rising Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500
μ
V/div
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