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參數(shù)資料
| 型號： | AD5533ABC-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | 32-Channel, 14-Bit Voltage-Output DAC |
| 中文描述： | SAMPLE AND HOLD AMPLIFIER, PBGA74 |
| 封裝： | 12 X 12 MM, LFBGA-74 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | AD5533ABC-1 |
AD5533
–13–
REV. 0
OFFSET SEL
A4
–
A0
CAL
0
0
MSB
LSB
MODE BIT 1
MODE BIT 2
MODE BITS
0
TEST BIT
a. 10-Bit Input Serial Write Word (SHA Mode)
OFFSET SEL
A4
–
A0
CAL
0
1
MSB
LSB
MODE BITS
DB13
–
DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF
SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
b. Input Serial Interface (Acquire and Readback Mode)
OFFSET SEL
A4
–
A0
0
1
1
MSB
LSB
MODE BITS
DB13
–
DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF
SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
c. Input Serial Interface (Readback Mode)
Figure 13. Serial Interface Formats
DB13–DB0
These are used in both readback modes to read a 14-bit word
from the addressed DAC register.
The serial interface is designed to allow easy interfacing to most
microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for
any glue logic. When interfacing to the 8051, the SCLK must
be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.
Figures 3 and 4 show the timing diagram for a serial read and
write to the AD5533. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of
SYNC
resets a counter that counts the number of serial
clocks to ensure the correct number of bits are shifted in and
out of the serial shift registers. Any further edges on
SYNC
are
ignored until the correct number of bits are shifted in or out.
Once the correct number of bits have been shifted in or out, the
SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of
SYNC
.
In readback, the first rising SCLK edge after the falling edge
of
SYNC
causes D
OUT
to leave its high impedance state and
data is clocked out onto the D
OUT
line and also on subsequent
SCLK rising edges. The D
OUT
pin goes back into a high imped-
ance state on the falling edge of the 14th SCLK. Data on the
D
IN
line is latched in on the first SCLK falling edge after the
falling edge of the
SYNC
signal and on subsequent SCLK falling
edges. The serial interface will not shift data in or out until it
receives the falling edge of the
SYNC
signal.
Parallel Interface
The SER/
PAR
bit must be tied low to enable the parallel inter-
face and disable the serial interface. The parallel interface is
controlled by nine pins.
CS
Active low package select pin. This pin is shared with the
SYNC
function for the serial interface.
WR
Active low write pin. The values on the address pins are latched
on a rising edge of
WR
.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed and the address on A4–A0 is ignored.
Cal
Same functionality as the Cal bit in the serial interface. When this
pin is high, all 32 channels acquire V
IN
simultaneously.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5533ABC-1REEL | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA T/R |
| AD5533ABCZ-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
| AD5533B | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Precision Infinite Sample-and-Hold |
| AD5533BBC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:32 CHANNEL, INFINITE SHA ONLY I.C. - Bulk |
| AD5533BBCZ-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
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