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參數(shù)資料
| 型號： | AD5532HSABC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| 中文描述： | SERIAL INPUT LOADING, 14-BIT DAC, PBGA74 |
| 封裝： | 12 X 12 MM, LFBGA-74 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 244K |
| 代理商： | AD5532HSABC |
REV. 0
AD5532
–12–
TRACK
V
IN
DAC
ACQUISITION
CIRCUIT
V
OUT
1
BUSY
OUTPUT
STAGE
CONTROLLER
THRESHOLD
VOLTAGE
PIN
DRIVER
DEVICE
UNDER
TEST
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
AD5532
Figure 18. Typical ATE Circuit Using
TRACK
Input
This is useful in an application where the user wants to ramp up
V
IN
until V
OUT
reaches a particular level (Figure 18). V
does
not need to be acquired continuously while it is ramping up.
TRACK
can be kept low and only when V
OUT
has reached its
desired voltage is
TRACK
brought high. At this stage, the
acquisition of V
IN
begins.
In the example shown, a desired voltage is required on the out-
put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on V
IN
through a DAC.
TRACK
is kept low
while the voltage on V
IN
ramps up so that V
IN
is not continu-
ally acquired. When the desired voltage is reached on the output
of the pin driver, the comparator output switches. The
μ
C/
μ
P
then knows what code is required to be input in order to obtain
the desired voltage at the DUT. The
TRACK
input is now
brought high and the part begins to acquire V
IN
. At this stage
BUSY
goes low until V
IN
has been acquired. The output buffer
is then switched from V
IN
to the output of the DAC.
MODES OF OPERATION
The AD5532 can be used in four different modes of opera-
tion. These modes are set by two mode bits, the first two bits in
the serial word.
Table II. Modes of Operation
Mode Bit 1
Mode Bit 2
Operating Mode
0
0
1
1
0
1
0
1
SHA Mode
DAC Mode
Acquire and Readback
Readback
1. DAC Mode
In this standard mode a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.
2. SHA Mode
In this mode a channel is addressed and that channel acquires
the voltage on V
IN
. This mode requires a 10-bit write (see Fig-
ure 21) to address the relevant channel (V
OUT
0–V
OUT
31, offset
channel or all channels) MSB is written first.
3. Acquire and Readback Mode
This mode allows the user to acquire V
IN
and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V
IN
is acquired in 16
μ
s (max).
Following the acquisition, after the next falling edge of
SYNC
,
the data in the relevant DAC register is clocked out onto the
D
OUT
line in a 14-bit serial format. The full acquisition time
must elapse before the DAC register data can be clocked out.
4. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of
SYNC
, the data in the relevant DAC
register is clocked out onto the D
OUT
line in a 14-bit serial format.
The user must allow 400 ns (min) between the last SCLK fall-
ing edge in the 10-bit write and the falling edge of
SYNC
in
the 14-bit readback. The serial write and read words can be
seen in Figure 19.
This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode this is useful in verification
of write cycles. In SHA mode readback is useful if the system
has been calibrated and the user wants to know what code in
the DAC corresponds to a desired voltage on V
OUT
. If the user
requires this voltage again, he can input the code directly to the
DAC register without going through the acquisition sequence.
INTERFACES
Serial Interface
The SER/
PAR
pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
SYNC
, D
IN
, SCLK
Standard 3-wire interface pins. The
SYNC
pin is shared
with the
CS
function of the parallel interface.
D
OUT
Data Out pin for reading back the contents of the DAC
registers. The data is clocked out on the rising edge of SCLK
and is valid on the falling edge of SCLK.
Mode Bits
There are four different modes of operation as described above.
Cal Bit
In DAC mode this is a test bit. When it is high it is used to load
all zeros or all ones to the 32DACs simultaneously. In SHA mode
all 32 channels acquire V
IN
simultaneously when this bit is high.
In SHA mode the acquisition time is then 45
μ
s (typ) and accu-
racy may be reduced. This bit is set low for normal operation.
Offset_Sel Bit
If this is set high, the offset channel is selected and Bits A4–
A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5532HSABCZ | 功能描述:IC DAC 14BIT 32CH HS 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5533 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Infinite Sample-and-Hold |
| AD5533ABC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
| AD5533ABC-1REEL | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA T/R |
| AD5533ABCZ-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
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