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參數(shù)資料
| 型號(hào)： | AD5532BBCZ-1 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 22µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 45k |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
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REV. A
AD5532B
–8–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
AGND (1–2)
Analog GND Pins
AVCC (1–2)
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VDD (1–4)
VDD Supply Pins. Voltage range from 8 V to 16.5 V.
VSS (1–4)
VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.
DGND
Digital GND Pins
DVCC
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
DAC_GND (1–2)
Reference GND Supply for all the DACs
REF_IN
Reference Voltage for Channels 0–31
REF_OUT
Reference Output Voltage
VOUT (0–31)
Analog Output Voltages from the 32 Channels
VIN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
A4–A1
1, A02
Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB.
CAL
1
Parallel Interface. Control input that allows all 32 channels to acquire VIN simultaneously.
CS/SYNC
This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for
the serial interface.
WR1
Parallel Interface. Write pin. Active low. This is used in conjunction with the
CS pin to address the device
using the parallel interface.
OFFSET_SEL
1
Parallel Interface. Offset select pin. Active high. This is used to select the offset channel.
SCLK
2
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
DIN
2
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
DOUT
Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid
on the falling edge of SCLK.
SER/
PAR1
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
OFFS_IN
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the offset channel.
OFFS_OUT
Offset Output. This is the acquired/programmed offset voltage that can be tied to OFFS_IN to offset the span.
BUSY
This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns
high when the acquisition operation is complete.
TRACK/RESET2
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge
of
TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going
pulse of between 90 ns and 200 ns to this pin. See section on
RESET Function for further details.
NOTES
1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
IDEAL TRANSFER
FUNCTION
IDEAL GAIN
REFIN
DAC CODE
OUTPUT
VOLTAGE
IDEAL GAIN
50mV
0
16k
FULL-SCALE
ERROR RANGE
OFFSET
RANGE
Figure 6. DAC Transfer Function (OFFS_IN = 0)
2.96 3V
70mV
0V
VOUT
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
GAIN ERROR +
OFFSET ERROR
VIN
UPPER
DEAD BAND
LOWER
DEAD BAND
Figure 7. ISHA Transfer Function
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5532HS | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| AD5532HSABC | 功能描述:IC DAC 14BIT 32CH 74-CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532HSABCZ | 功能描述:IC DAC 14BIT 32CH HS 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5533 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Infinite Sample-and-Hold |
| AD5533ABC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
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