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參數(shù)資料
| 型號(hào)： | AD5532BBC-1 |
| 元件分類(lèi)： | 取樣保持放大器 |
| 英文描述： | SAMPLE/TRACK-AND-HOLD AMPLIFIER|32-CHANNEL|CMOS|BGA|74PIN|PLASTIC |
| 中文描述： | 采樣/跟蹤和保持放大器| 32-CHANNEL |的CMOS | BGA封裝| 74PIN |塑料 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 569K |
| 代理商： | AD5532BBC-1 |
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REV. A
–4–
AD5532B-1
B Version
2
Parameter
1
DAC AC CHARACTERISTICS
3
Output Voltage Settling Time
OFFS_IN Settling Time
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
Unit
Conditions/Comments
22
10
1
5
1
0.2
400
μ
s max
μ
s max
nV-s
typ
nV-s
typ
nV-s
typ
nV-s
typ
nV/
√
Hz
typ
500 pF, 5 k
Load Full-Scale Change
500 pF, 5 k
Load; 0 V to 3 V Step
1 LSB Change Around Major Carry
ISHA AC CHARACTERISTICS
Output Voltage Settling Time
3
Acquisition Time
AC Crosstalk
3
3
16
5
μ
s max
μ
s max
nV-s
typ
Outputs Unloaded
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range –40
°
C to +85
°
C; typical at +25
°
C.
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change
without notice.
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Limit at T
MIN
, T
MAX
Parameter
1, 2
(B Version)
Unit
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
0
0
50
50
20
7
ns min
ns min
ns min
ns min
ns min
ns min
CS
to
WR
Setup Time
CS
to
WR
Hold Time
CS
Pulsewidth Low
WR
Pulsewidth Low
A4–A0, CAL, OFFS_SEL to
WR
Setup Time
A4–A0, CAL, OFFS_SEL to
WR
Hold Time
NOTES
1
See Parallel Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at T
MIN
, T
MAX
(B Version)
Parameter
1, 2
f
CLKIN3
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
84
t
94
t
10
t
t
11
Unit
Conditions/Comments
14
28
28
15
50
15
5
5
20
60
400
400
7
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC
Falling Edge to SCLK Falling Edge Setup Time
SYNC
Low Time
D
IN
Setup Time
D
IN
Hold Time
SYNC
Falling Edge to SCLK Rising Edge Setup Time for Readback
SCLK Rising Edge to D
OUT
Valid
SCLK Falling Edge to D
OUT
High Impedance
10th SCLK Falling Edge to
SYNC
Falling Edge for Readback
24th SCLK Falling Edge to
SYNC
Falling Edge for DAC Mode Write
SCLK Falling Edge to
SYNC
Falling Edge for Readback
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4
These numbers are measured with the load circuit of Figure 2.
5
SYNC
should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
AD5532B
AC CHARACTERISTICS
(V
DD
= +8 V to +16.5 V, V
SS
= –4.75 V to –16.5 V; AV
CC
= +4.75 V to +5.25 V; DV
CC
= +2.7 V to +5.25 V;
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications T
MIN
to T
MAX
, unless otherwise noted.)
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