參數(shù)資料
型號: AD5532ABCZ-5
廠商: Analog Devices Inc
文件頁數(shù): 1/20頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CH BIPO 74-CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設(shè)置時間: 22µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 34
電壓電源: 模擬和數(shù)字
功率耗散(最大): 623mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 74-LBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 74-CSPBGA(12x12)
包裝: 托盤
輸出數(shù)目和類型: 32 電壓,單極
采樣率(每秒): 45k
配用: EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS
EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532
32-Channel, 14-Bit
Voltage-Output DAC
AD5532
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2010 Analog Devices, Inc. All rights reserved.
FEATURES
High integration:
32-channel DAC in 12 mm × 12 mm CSPBGA
Adjustable voltage output range
Guaranteed monotonic
Readback capability
DSP/microcontroller compatible serial interface
Output impedance:
0.5 Ω (AD5532-1, AD5532-2)
500 Ω (AD5532-3)
1 kΩ (AD5532-5)
Output voltage span:
10 V (AD5532-1, AD5532-3, AD5532-5)
20 V (AD5532-2)
Infinite sample-and-hold capability to ±0.018% accuracy
Temperature range
40°C to +85°C
APPLICATIONS
Automatic test equipment
Optical networks
Level setting
Instrumentation
Industrial control systems
Data acquisition
Low cost I/O
GENERAL DESCRIPTION
The AD55321 is a 32-channel, 14-bit voltage-output DAC with
an additional infinite sample-and-hold mode. The selected
DAC register is written to via the 3-wire serial interface; VOUT
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via Address Bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from VSS + 2 V to VDD – 2 V because of
the headroom of the output amplifier.
The device is operated with AVCC = 5 V ± 5%; DVCC = 2.7 V to
5.25 V; VSS = 4.75 V to 16.5 V; and VDD = 8 V to 16.5 V. The
AD5532 requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1.
32-channel, 14-bit DAC in one package, guaranteed
monotonic.
2.
Available in a 74-lead CSPBGA package with a body size of
12 mm ×12 mm.
3.
Droopless/infinite sample-and-hold mode.
00939-C-001
SCLK DIN DOUT
A4–A0
CAL
OFFSET_SEL
AD5532
ADDRESS INPUT REGISTER
DAC
ADC
MUX
DAC
MO
DE
1
4
-BIT
BUS
VIN
TRACK/RESET
BUSY
DAC_GND
AGND
DGND
INTERFACE
CONTROL
LOGIC
SER/PAR
DVCC
VOUT0
OFFS_OUT
VOUT31
AVCC
REF_IN
REF_OUT
OFFS_IN
VDD
VSS
WR
SYNC/CS
Figure 1. Functional Block Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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