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參數(shù)資料
| 型號(hào)： | AD5532ABCZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 30µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 45k |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
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AD5532
Rev. D | Page 16 of 20
SERIAL INTERFACE
The serial interface allows easy interfacing to most micro-
controllers and DSPs, such as the PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for any
glue logic. When interfacing to the 8051, the SCLK must be
inverted. The Microprocessor Interfacing section explains how
to interface to some popular DSPs and microcontrollers. Figure
4, Figure 5, and Figure 6 show the timing diagram for a serial
read and write to the AD5532. The serial interface works with
both a continuous and a noncontinuous serial clock. The first
falling edge of SYNC resets a counter that counts the number of
serial clocks to ensure the correct number of bits are shifted in
and out of the serial shift registers. Any further edges on SYNC
are ignored until the correct number of bits are shifted in or
out. Once the correct number of bits for the selected mode has
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place the counter must be reset by the
falling edge of SYNC.
In readback, the first rising SCLK edge after the falling edge of
SYNC causes DOUT to leave its high impedance state and data is
clocked out onto the DOUT line and also on subsequent SCLK
rising edges. The DOUT pin goes back into a high impedance
state on the falling edge of the 14th SCLK. Data on the DIN line
is latched in on the first SCLK falling edge after the falling edge
of the SYNC signal and on subsequent SCLK falling edges.
During read-back DIN is ignored. The serial interface does
not shift data in or out until it receives the falling edge of the
SYNC signal.
Table 10
Pin
Description
SER/PAR
This pin is tied high to enable the serial interface
and to disable the parallel interface. The serial
interface is controlled by the four pins that follow.
SYNC,
DIN, SCLK
Standard 3-wire interface pins. The SYNC pin is
shared with the CS function of the parallel interface.
DOUT
Data Out pin for reading back the contents of the
DAC registers. The data is clocked out on the rising
edge of SCLK and is valid on the falling edge of
SCLK.
Mode
Bits
The four different modes of operation are described
in the Modes of Operation section.
Cal Bit
In DAC mode, this is a test bit. When high, it loads all
0s or all 1s to the 32 DACs simultaneously. In ISHA
mode, all 32 channels acquire VIN at the same time
when this bit is high. In ISHA mode, the acquisition
time is then 45 μs (typ) and accuracy may be
reduced. This bit is set low for normal use.
Offset Sel
Bit
If this is set high, the offset channel is selected and
Bits A4–A0 are ignored.
Test Bit
Must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels
(A4 = MSB of address, A0 = LSB).
DB13–
DB0
Used to write a 14-bit word into the addressed DAC
register. Only valid when in DAC mode.
00939-C-020
OFFSET_SEL
A4–A0
CAL
0
MSB
LSB
MODE BIT 1
MODE BIT 2
MODE BITS
0
TEST BIT
OFFSET_SEL
A4–A0
CAL
1
0
MSB
LSB
MODE BITS
DB13–DB0
0
TEST BIT
a. 10-BIT SERIAL WRITE WORD (ISHA MODE)
b. 24-BIT INPUT SERIAL WRITE WORD (DAC MODE)
c. INPUT SERIAL INTERFACE (ACQUIRE AND READ-BACK MODE)
d. INPUT SERIAL INTERFACE (READ-BACK MODE)
OFFSET_SEL
A4–A0
CAL
0
1
MSB
LSB
MODE BITS
DB13–DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
OFFSET_SEL
A4–A0
CAL
1
MSB
LSB
MODE BITS
DB13–DB0
0
TEST BIT
MSB
LSB
Figure 21. Serial Interface Formats
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| AD5532ABCZ-3 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5532ABCZ-5 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD5532B: 32-Channel. 14-Bit DAC with Precision Infinite Sample-and-Hold Mode (Rev A. 9/02) |
| AD5532BBC-1 | 制造商:Analog Devices 功能描述:DAC 32-CH 14-bit 74-Pin CSP-BGA Tray 制造商:Rochester Electronics LLC 功能描述:32 CHANNEL, 14-BIT DAC & SHA I.C. - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty |
| AD5532BBCZ-1 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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