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| 型號(hào)： | AD5516ABC-2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode |
| 中文描述： | SERIAL INPUT LOADING, 14-BIT DAC, PBGA74 |
| 封裝： | 12 X 12 MM, MO-192ABD-1, CSPBGA-74 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | AD5516ABC-2 |
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–3–
AC CHARACTERISTICS
AD5516
(V
DD
= +4.75 V to +13.2 V, V
SS
= –4.75 V to –13.2 V; AV
CC
= 4.75 V to 5.25 V; DV
CC
= 2.7 V to 5.25 V; AGND = DGND
= DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
1, 2
Output Voltage Settling Time (Mode 1)
4
Output Voltage Settling Time (Mode 2)
4
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk AD5516-1
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
A Version
3
Unit
Conditions/Comments
100 pF, 5 k
Load Full-Scale Change
100 pF, 5 k
Load, 1 Code Increment
32
2.5
0.85
1
5
10
1
150
s max
s max
V/ s typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)
1/2
typ
1 LSB Change around Major Carry
AD5516-1
NOTES
1
See Terminology section.
2
Guaranteed by design and characterization; not production tested.
3
A version: Industrial temperature range –40
°
C to +85
°
C.
4
Timed from the end of a write sequence.
Specifications subject to change without notice.
Limit at T
MIN
, T
MAX
(A Version)
Parameter
1, 2, 3
Unit
Conditions/Comments
f
UPDATE1
f
UPDATE2
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
7MODE2
t
8MODE1
t
9MODE2
t
10
t
114
t
12
32
750
20
20
20
15
5
5
0
10
400
10
200
10
20
20
kHz max
kHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
DAC Update Rate (Mode 1)
DAC Update Rate (Mode 2)
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC
Falling Edge to SCLK Falling Edge Setup Time
D
IN
Setup Time
D
IN
Hold Time
SCLK Falling Edge to
SYNC
Rising Edge
Minimum
SYNC
High Time (Standalone Mode)
Minimum
SYNC
High Time (Daisy-Chain Mode)
BUSY
Rising Edge to
SYNC
Falling Edge
18th SCLK Falling Edge to
SYNC
Falling Edge (Standalone Mode)
SYNC
Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
SCLK Rising Edge to D
OUT
Valid (Daisy-Chain Mode)
RESET
Pulsewidth
NOTES
1
See Timing Diagrams in Figures 1 and 2.
2
Guaranteed by design and characterization; not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
4
This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(V
DD
= +4.75 V to +13.2 V, V
SS
= – 4.75 V to –13.2 V; AV
CC
= 4.75 V to 5.25 V; DV
CC
= 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
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