參數(shù)資料
型號(hào)： AD5449YRU-REEL
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述： SERIAL INPUT LOADING, 0.08 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝： MO-153AB, TSSOP-16
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 860K
代理商： AD5449YRU-REEL
AD5429/AD5439/AD5449
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 32
1
2
3
4
5
6
7
8
NC = NO CONNECT
16
15
14
13
12
11
10
9
I
OUT
2A
R
FB
A
V
REF
A
SCLK
LDAC
GND
I
OUT
1A
I
OUT
2B
R
FB
B
V
REF
B
SYNC
SDIN
SDO
CLR
V
DD
I
OUT
1B
AD5429/
AD5439/
AD5449
TOP VIEW
(Not to Scale)
0
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Function
1
I
OUT
1A
2
I
OUT
2A
DAC A Current Output.
DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
DAC A Reference Voltage Input Pin.
Ground Pin.
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous
update mode is selected whereby the DAC is updated on the 16th clock falling edge when the device is in
standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on
the active edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched
to the shift register on the16th active clock edge.
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear to zero scale or midscale as required.
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B Reference Voltage Input Pin.
DAC B Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC B Current Output.
3
4
5
6
R
FB
A
V
REF
A
GND
LDAC
7
SCLK
8
SDIN
9
SDO
10
SYNC
11
CLR
12
13
14
15
V
DD
V
REF
B
R
FB
B
I
OUT
2B
16
I
OUT
1B
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