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參數(shù)資料
| 型號： | AD5446YRM-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT MULTIPLYING 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151) |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.7M |
| 配用： | EVAL-AD5446EBZ-ND - BOARD EVALUATION FOR AD5446 |
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AD5444/AD5446
Data Sheet
Rev. E | Page 16 of 28
Bipolar Operation
In some applications, it may be necessary to generate a full
4-quadrant multiplying operation, or a bipolar output swing.
This can easily be accomplished by using another external
amplifier and some external resistors, as shown in Figure 39.
In this circuit, the second amplifier (A2) provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in a full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = VREF) to midscale
(VOUT 0 V) to full scale (VOUT = +VREF)
REF
n
REF
OUT
V
D
V
×
=
1
2
where:
D is the fractional representation of the digital word loaded
to the DAC:
D = 0 to 4095 (12-bit AD5444)
D = 0 to 16383 (14-bit AD5446)
n is the resolution of the DAC.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code
Digital Input
Analog Output (V)
1111 1111 1111
+VREF (2047/2048)
1000 0000 0000
0
0000 0000 0001
VREF (2047/2048)
0000 0000 0000
VREF (0/2048)
Stability
In the current-to-voltage (I-to-V) configuration, the IOUT1of the
DAC and the inverting node of the op amp must be connected
as closely as possible, and proper PCB layout techniques must
be employed. Because every code change corresponds to a step
function, gain peaking can occur if the op amp has limited GBP
and excessive parasitic capacitance exists at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response that can cause ringing or instability in the closed-loop
applications circuit.
An optional compensation capacitor (C1) can be added in
Figure 39. Too small a value for C1 can produce ringing at
the output, while too large a value can adversely affect the
settling time. C1 should be found empirically, but 1 pF to
2 pF is generally adequate for the compensation.
04588-
031
IOUT1
IOUT2
AD5444/
AD5446
VREF
VDD
C1
A1
VOUT = –VREF TO +VREF
AGND
R2
VDD
VREF ±10V
SDIN
SCLK
SYNC
MICROCONTROLLER
A2
R4
10k
R5
20k
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
R3 AND R4.
R3
20k
R1
RFB
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
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