Data Sheet
AD5424/AD5433/AD5445
Rev. D | Page 3 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: 40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance measured wit
h OP177 and ac performance measured wit
h AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
STATIC PERFORMANCE
Resolution
8
Bits
Relative Accuracy
±0.25
LSB
Differential Nonlinearity
±0.5
LSB
Guaranteed monotonic
Resolution
10
Bits
Relative Accuracy
±0.5
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
Resolution
12
Bits
Relative Accuracy
±1
LSB
Differential Nonlinearity
–1/+2
LSB
Guaranteed monotonic
Gain Error
±10
mV
Gain Error Temperature Coefficie
nt1±5
ppm FSR/°C
±10
nA
Data = 0×0000, TA = 25°C, IOUT1
±20
nA
Data = 0×0000, T = 40°C to +125°C, IOUT1
Reference Input Range
±10
V
VREF Input Resistance
8
10
12
k
Input resistance TC = –50 ppm/°C
RFB Resistance
8
10
12
k
Input resistance TC = –50 ppm/°C
Input Capacitance
Code Zero Scale
3
6
pF
Code Full Scale
5
8
pF
Input High Voltage, VIH
1.7
V
Input Low Voltage, VIL
0.6
V
Output High Voltage, VOH
VDD 1
V
VDD = 4.5 V to 5 V, ISOURCE = 200 A
VDD 0.5
V
VDD = 2.5 V to 3.6 V, ISOURCE = 200 A
Output Low Voltage, VOL
0.4
V
VDD = 4.5 V to 5 V, ISINK = 200 A
0.4
V
VDD = 2.5 V to 3.6 V, ISINK = 200 A
Input Leakage Current, IIL
1
A
Input Capacitance
4
10
pF
Reference Multiplying Bandwidth
10
MHz
VREF = ±3.5 V; DAC loaded all 1s
Output Voltage Settling Time
VREF = ±3.5 V, RLOAD = 100 , DAC latch
alternately loaded with 0s and 1s
Measured to ±16 mV of full scale
30
60
ns
Measured to ±4 mV of full scale
35
70
ns
Measured to ±1 mV of full scale
80
120
ns
Digital Delay
20
40
ns
Interface delay time
10% to 90% Settling Time
15
30
ns
Rise and fall time, VREF = 10 V, RLOAD = 100
Digital-to-Analog Glitch Impulse
2
nV-s
1 LSB change around major carry, VREF = 0 V
Multiplying Feedthrough Error
DAC latch loaded with all 0s, VREF = ±3.5 V
70
dB
Reference = 1 MHz
48
dB
Reference = 10 MHz