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參數(shù)資料
| 型號： | AD5445 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface |
| 中文描述： | 8-/10-/12-Bit，高帶寬，乘以并行接口數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 888K |
| 代理商： | AD5445 |
REV. 0
–2–
AD5424/AD5433/AD5445–SPECIFICATIONS
1
(V
= 2.5 V to 5.5 V, V
= 10 V, I
2 = O V. All specifications T
MIN
to T
MAX
, unless otherwise noted. DC performance measured with OP1177,
AC performance with AD8038, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5424
Resolution
Relative Accuracy
Differential Nonlinearity
AD5433
Resolution
Relative Accuracy
Differential Nonlinearity
AD5445
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
2
Output Leakage Current
2
8
±
0.25
±
0.5
Bits
LSB
LSB
Guaranteed monotonic
10
±
0.5
±
1
Bits
LSB
LSB
Guaranteed monotonic
12
±
1
–1/+2
±
10
Bits
LSB
LSB
mV
ppm FSR/ C
nA
nA
Guaranteed monotonic
±
5
±
10
±
20
Data = 0x0000, T
A
= 25 C, I
OUT
1
Data = 0x0000, I
OUT
1
REFERENCE INPUT
2
Reference Input Range
V
REF
Input Resistance
R
FB
Resistance
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
2
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Leakage Current, I
IL
Input Capacitance
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
Output High Voltage, V
OH
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
Output High Voltage, V
OH
DYNAMIC PERFORMANCE
2
Reference Multiplying Bandwidth
Output Voltage Settling Time
AD5424
AD5433
AD5445
Digital Delay
10%
to 90% Settling Time
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
±
10
10
10
V
k
k
8
8
12
12
Input resistance TC = –50 ppm/ C
Input resistance TC = –50 ppm/ C
3
5
6
8
pF
pF
1.7
V
V
0.6
1
10
A
4
pF
0.4
V
V
I
SINK
= 200
μ
A
I
SOURCE
= 200
μ
A
V
DD
– 1
0.4
V
V
I
SINK
= 200
μ
A
I
SOURCE
= 200
μ
A
V
DD
– 0.5
10
MHz
V
REF
=
±
3.5 V; DAC loaded all 1s
V
REF
= 10 V, R
LOAD
= 100
, C
LOAD
= 15 pF
Measured to
±
16 mV of full scale
Measured to
±
4 mV of full scale
Measured to
±
1 mV of full scale
Interface delay time
Rise and Fall time, V
REF
= 10 V, R
LOAD
= 100
1 LSB change around major carry, V
REF
= 0 V
DAC latch loaded with all 0s. V
REF
=
3.5 V
Reference = 1 MHz
Reference = 10 MHz
30
35
80
20
15
2
60
70
120
40
30
ns
ns
ns
ns
ns
nV-s
70
48
dB
dB
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