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參數(shù)資料
| 型號(hào)： | AD5444YRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 28/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SERIAL OUT 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 16ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.7M |
| 產(chǎn)品目錄頁(yè)面： | 782 (CN2011-ZH PDF) |
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Data Sheet
AD5444/AD5446
Rev. E | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04588-
005
10
9
8
7
6
1
2
3
4
5
IOUT1
IOUT2
GND
SCLK
SDIN
RFB
VREF
VDD
SDO
AD5444/
AD5446
TOP VIEW
(Not to Scale)
SYNC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1
DAC Current Output.
2
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to the rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low,
data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising
edge of SYNC.
7
SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to data loaded to the shift register.
8
VDD
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
9
VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.
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| AD5444YRMZ-REEL | 功能描述:IC DAC 12BIT MULTIPLYING 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5444YRMZ-REEL7 | 功能描述:IC DAC 12BIT MULTIPLYING 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5445 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5445YCP | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12-BIT LOUT DAC PARELLED INT/FACE I.C. - Bulk 制造商:Analog Devices 功能描述:12BIT DAC PARALLEL I/F SMD 5445 |
| AD5445YCP-REEL | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 20-Pin LFCSP EP T/R |
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