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| 型號(hào)： | AD5444 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 中文描述： | 雙8 - ，10 - 12位高帶寬倍增DAC的串行接口 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大小： | 860K |
| 代理商： | AD5444 |
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AD5429/AD5439/AD5449
REFERENCE SELECTION
When selecting a reference for use with the AD5429/AD5439/
AD5449 family of current output DACs, pay attention to the
reference’s output voltage temperature coefficient specification.
This parameter affects not only the full-scale error, but also
the linearity (INL and DNL) performance. The reference
temperature coefficient should be consistent with the system
accuracy specifications. For example, an 8-bit system required
to hold its overall specification to within 1 LSB over the
temperature range 0°C to 50°C dictates that the maximum
system drift with temperature should be less than 78 ppm/°C.
A 12-bit system with the same temperature range to overall
specification within 2 LSBs requires a maximum drift of
10 ppm/°C. By choosing a precision reference with low output
temperature coefficient, this error source can be minimized.
Table 7 lists some of the references available from Analog
Devices that are suitable for use with this range of current
output DACs.
Rev. 0 | Page 19 of 32
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input bias current of an op amp also
generates an offset at the voltage output as a result of the bias
current flowing in the feedback resistor R
FB
. Most op amps have
input bias currents low enough to prevent any significant errors
in 12-bit applications.
Common-mode rejection of the op amp is important in
voltage-switching circuits, because it produces a code-
dependent error at the voltage output of the circuit. Most
op amps have adequate common-mode rejection for use at
8-, 10-, and 12-bit resolution.
Provided that the DAC switches are driven from true wideband
low impedance sources (V
IN
and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-
switching DAC circuit is determined largely by the output
op amp. To obtain minimum settling time in this configuration,
it is important to minimize capacitance at the V
REF
node
(voltage output node in this application) of the DAC. This is
done by using low input capacitance buffer amplifiers and
careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. Analog Devices supplies a large range
of single-supply amplifiers.
Table 7. Suitable ADI Precision References Recommended for Use with AD5429/AD5439/AD5449 DACs
Reference
Output Voltage
Initial Tolerance
ADR01
10 V
0.1%
ADR02
5 V
0.1%
ADR03
2.5 V
0.2%
ADR425
5 V
0.04%
Temperature Drift
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
0.1 Hz to 10 Hz Noise
20 μV p-p
10 μV p-p
10 μV p-p
3.4 μV p-p
Package
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table 8. Precision ADI Op Amps Suitable for Use with AD5429/AD5439/AD5449 DACs
Part No.
Max Supply Voltage (V)
OP97
±20
OP1177
±18
AD8551
±6
V
OS
(max) μV
25
60
5
I
B
(max) nA
0.1
2
0.05
GBP MHz
0.9
1.3
1.5
Slew Rate V/μs
0.2
0.7
0.4
Table 9. High Speed ADI Op Amps Suitable for Use with AD5429/AD5439/AD5449 DACs
Part No.
Max Supply Voltage (V)
AD8065
±12
AD8021
±12
AD8038
±5
BW @ A
CL
(MHz)
145
200
350
Slew Rate (V/μs)
180
100
425
V
OS
(max) μV
1500
1000
3000
I
B
max (nA)
0.01
1000
0.75
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