參數(shù)資料
型號(hào): AD5441BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 15/17頁(yè)
文件大小: 0K
描述: IC DAC 12BIT SERIAL IN 8LFCSP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 500ns
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 8-LFCSP-WD(3x3)
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 5M
產(chǎn)品目錄頁(yè)面: 782 (CN2011-ZH PDF)
配用: EVAL-AD5541/42EBZ-ND - BOARD EVAL FOR AD5441/2
其它名稱: AD5441BCPZ-REEL7DKR
AD5441
Rev. A | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
06
49
2-
00
3
AD5441
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
1
VREF
2
RFB
3
IOUT
4
GND
7CLK
8VDD
6SRI
5LD
NOTES
1. THE EXPOSED PAD SHOULD BE
CONNECTED TO THE GROUND PLANE.
Figure 5. 8-Lead LFCSP Pin Configuration
1
2
3
4
8
7
6
5
AD5441
TOP VIEW
(Not to Scale)
064
92
-00
4
IOUT
GND
RFB
VREF
VDD
CLK
SRI
LD
Figure 6. 8-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VREF
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
2
RFB
Internal Matching Feedback Resistor. Connect to external op amp output.
3
IOUT
DAC Current Output, full-scale output 1 LSB less than reference input voltage VREF.
4
GND
Analog and Digital Ground.
5
LD
Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low.
See Table 3 for operation.
6
SRI
12-Bit Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
7
CLK
Clock Input. Positive-edge clocks data into shift register.
8
VDD
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
EP
Exposed Pad. The exposed pad should be connected to the ground plane.
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