參數(shù)資料
型號(hào): AD5439YRU-REEL
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述: SERIAL INPUT LOADING, 0.08 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝: ROHS COMPLIANT, MO-153AB, TSSOP-16
文件頁數(shù): 6/32頁
文件大?。?/td> 860K
代理商: AD5439YRU-REEL
AD5429/AD5439/AD5449
Rev. 0 | Page 6 of 32
t
1
t
2
t
3
t
7
t
8
t
4
t
5
t
6
t
9
t
10
t
11
DB15
DB0
SCLK
DIN
LDAC
1
LDAC
2
SYNC
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
0
Figure 2. Standalone Mode Timing Diagram
0
t
8
t
7
t
12
t
1
t
3
t
2
t
4
t
5
t
6
DB15
(N)
DB15
(N+1)
DB0
(N)
DB0
(N+1)
DB15
(N)
DB0
(N)
SCLK
SYNC
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200
μ
A
I
OL
200
μ
A
I
OH
TO OUTPUT
PIN
C
L
50pF
V
OH
(MIN) + V
OL
(MAX)
2
0
Figure 4. Load Circuit for SDO Timing Specifications
相關(guān)PDF資料
PDF描述
AD5449YRU-REEL Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5439YRU-REEL7 Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5449YRU-REEL7 Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5449YRU Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
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